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MC92610UM/D 3/2003 Rev. 1
MC92610 Quad 3.125 Gbaud SERDES User's Manual
Device Supported: MC92610VF
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003
Overview Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
1 2 3 4 5 6 7
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
A B GLO IND
1 2 3 4 5 6 7
Overview Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
A B GLO IND
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
Contents
Paragraph Section Number Title About This Book Audience .............................................................................................................. xiii Organization......................................................................................................... xiii Suggested Reading............................................................................................... xiv General Information..................................................................................... xiv Related Documentation ............................................................................... xiv Conventions ...........................................................................................................xv Signals....................................................................................................................xv Chapter 1 Introduction 1.1 1.2 1.3 1.4 1.5 Overview.............................................................................................................. 1-1 Features ................................................................................................................ 1-1 Block Diagram ..................................................................................................... 1-2 References............................................................................................................ 1-4 Revision History .................................................................................................. 1-4 Chapter 2 Transmitter 2.1 2.2 2.3 2.3.1 2.3.1.1 2.3.1.2 2.3.1.3 2.3.1.4 2.3.1.5 2.3.1.6 2.3.1.7 2.3.1.8 2.3.1.9 Block Diagram ..................................................................................................... 2-1 Transmitter Interface Signals ............................................................................... 2-2 Functional Description......................................................................................... 2-5 Transmit Data Input Register Operation.......................................................... 2-5 Transmitting Uncoded Data......................................................................... 2-5 Transmitting Pre-Coded Data ...................................................................... 2-6 Link Multiplexer Mode................................................................................ 2-6 Repeater Mode............................................................................................. 2-7 Transmit Interface Clock Configuration...................................................... 2-7 8B/10B Encoder Operation.......................................................................... 2-7 Transmit Driver Operation........................................................................... 2-8 Transmit Equalization.................................................................................. 2-8 Loop-Back Test Mode ................................................................................. 2-9 Page Number
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Contents
Paragraph Number Title Chapter 3 Receiver 3.1 3.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.2 3.3.3 3.3.3.1 3.3.3.2 3.3.4 3.3.4.1 3.3.4.2 3.3.4.3 3.3.4.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.7 3.3.7.1 3.3.7.2 3.3.8 3.3.9 3.3.10 Receiver Block Diagram...................................................................................... 3-1 Receiver Interface Signals ................................................................................... 3-2 Receiver Functional Description ......................................................................... 3-5 Input Amplifier ................................................................................................ 3-6 Receiver Equalization.................................................................................. 3-7 Loop-Back Test Mode ................................................................................. 3-7 Transition Tracking Loop and Data Recovery................................................. 3-8 Byte Alignment................................................................................................ 3-8 Byte Alignment and Realignment Method .................................................. 3-8 Non-Aligned Method................................................................................... 3-9 Word Synchronization ..................................................................................... 3-9 Word Synchronization Method.................................................................. 3-10 Word Synchronization Bus ........................................................................ 3-11 Multi-Chip Word Synchronization ............................................................ 3-11 Recommended Mode States for Word Synchronization............................ 3-12 8B/10B Decoder ............................................................................................ 3-13 Receiver Interface .......................................................................................... 3-13 Byte Interface............................................................................................. 3-14 Ten-Bit Interface ........................................................................................ 3-14 Receiver Interface Error Codes ................................................................. 3-14 Receiver Interface Clock Timing Modes....................................................... 3-15 Recovered Clock Timing Mode................................................................. 3-16 Reference Clock Timing Mode.................................................................. 3-16 Half-Speed Mode........................................................................................... 3-17 Repeater Mode............................................................................................... 3-17 Link Multiplexer Mode.................................................................................. 3-17 Chapter 4 System Design Considerations 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6
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Reference Clock Configuration ........................................................................... 4-1 Startup .................................................................................................................. 4-2 Repeater Mode ..................................................................................................... 4-2 Ten-Bit Interface Mode.................................................................................... 4-2 Byte Alignment Mode ..................................................................................... 4-3 Word Synchronization Mode ........................................................................... 4-3 Recovered Clock Timing Mode....................................................................... 4-3 Reference Clock Timing Mode........................................................................ 4-4 Half-Speed Mode, Double Data Rate Mode.................................................... 4-4
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Contents
Paragraph Number 4.4 4.5 4.6 4.7 4.8 4.8.1 4.9 Title Page Number
Configuration and Control Signals ...................................................................... 4-4 Power Supply Requirements................................................................................ 4-5 Phase Locked Loop (PLL) Power Supply Filtering............................................. 4-5 Power Supply Decoupling Recommendations .................................................... 4-6 HSTL Reference Voltage Recommendation........................................................ 4-6 Voltage Reference for Single-Ended Reference Clock Use............................. 4-7 Impedance Control Reference Recommendation ................................................ 4-7 Chapter 5 Test Features
5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.2 5.2.1 5.2.2 5.3
IEEE Std. 1149.1 Implementation ....................................................................... 5-1 Test Access Port (TAP) Interface Signals ........................................................ 5-1 Instruction Register.......................................................................................... 5-2 Instructions....................................................................................................... 5-2 Boundary-Scan Register .................................................................................. 5-3 Device Identification Register (0x0280E01D) ................................................ 5-3 Performance ..................................................................................................... 5-3 System Accessible Test Modes ............................................................................ 5-3 Loop Back System Test ................................................................................... 5-4 BIST Sequence System Test Mode.................................................................. 5-4 Loop-Back BIST Sequence System Test Mode................................................... 5-6 Chapter 6 Electrical Specifications and Characteristics
6.1 6.1.1 6.1.2 6.1.3 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6
General Characteristics ........................................................................................ 6-1 General Parameters .......................................................................................... 6-1 Absolute Maximum Ratings ............................................................................ 6-1 Recommended Operating Conditions.............................................................. 6-2 DC Electrical Specifications ................................................................................ 6-3 AC Electrical Characteristics............................................................................... 6-4 Parallel Port Interface Timing.......................................................................... 6-4 Word Synchronization Bus Timing.................................................................. 6-6 Reference Clock Timing .................................................................................. 6-7 Receiver Recovered Clock Timing.................................................................. 6-8 Serial Data Link Timing .................................................................................. 6-9 JTAG Test Port Timing .................................................................................. 6-10
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Contents
Chapter 7 Package Description 7.1 7.2 7.3 7.4 324 MAPBGA Package Parameter Summary ..................................................... 7-1 Nomenclature and Dimensions of the 324 MAPBGA Package .......................... 7-1 Package Thermal Characteristics......................................................................... 7-5 MC92610 Chip Pinout Listing............................................................................. 7-5 Appendix A Ordering Information Appendix B 8B/10B Coding Scheme B.1 B.1.1 B.1.2 B.1.3 B.2 Overview..............................................................................................................B-1 Naming Transmission Characters ....................................................................B-2 Encoding ..........................................................................................................B-2 Calculating Running Disparity ........................................................................B-3 Data Tables...........................................................................................................B-3 Glossary of Terms and Abbreviations Index
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Figures
Figure Number 1-1 2-1 3-1 4-1 4-2 4-3 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 7-1 7-2 7-3 A-1 B-1 B-2 B-3 Title Page Number
MC92610 Block Diagram ........................................................................................... 1-3 MC92610 Transmitter Block Diagram ....................................................................... 2-2 MC92610 Receiver Block Diagram............................................................................ 3-2 PLL Power Supply Filter Circuits............................................................................... 4-6 HSTL Class-I VREF Circuit ....................................................................................... 4-7 Impedance Reference Circuit...................................................................................... 4-8 Instruction Register ..................................................................................................... 5-2 Device Identification Register .................................................................................... 5-3 Transmitter DDR Interface Timing............................................................................. 6-4 Transmitter Interface SDR Timing Diagram (LME = High, DDRE = Low).............. 6-5 Receiver Interface DDR Timing Diagram .................................................................. 6-5 Receiver Interface SDR Timing Diagram (LME = High, DDRE = Low) .................. 6-6 Word Synchronization Bus Timing Diagram.............................................................. 6-7 Reference Clock Timing Diagram .............................................................................. 6-7 Recovered Clock Timing Diagram ............................................................................. 6-8 Link Differential Output Timing Diagram.................................................................. 6-9 Link Differential Input Timing Diagram .................................................................... 6-9 JTAG I/O Timing Diagram ....................................................................................... 6-10 324 MAPBGA Nomenclature ..................................................................................... 7-2 MAPBGA Dimensions ............................................................................................... 7-3 324 MAPBGA Package .............................................................................................. 7-4 Motorola Part Number Key........................................................................................ A-1 Unencoded Transmission Character Bit Ordering ......................................................B-1 Encoded Transmission Character Bit Ordering ..........................................................B-2 Character Transmission...............................................................................................B-3
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Figures
ix
Figures
Figure Number Title Page Number
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Tables
Table Number 1-1 2-1 2-2 3-1 3-2 3-3 3-4 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 7-1 7-2 B-1 B-2 B-3 Title Page Number
MC92610 SERDES User's Manual Revision History................................................ 1-4 MC92610 Transmitter Interface Signals ..................................................................... 2-3 Transmitter Control States .......................................................................................... 2-6 Receiver Interface Signals ......................................................................................... 3-3 Word Synchronization States .................................................................................... 3-12 Receiver Interface Error Codes (Byte Interface) ...................................................... 3-15 Receiver Interface Error Codes (Ten-Bit Interface).................................................. 3-15 Legal Reference Clock Frequency Ranges ................................................................. 4-1 Startup Sequence Step Duration.................................................................................. 4-2 Asynchronous Configuration and Control Signals ..................................................... 4-4 TAP Interface Signals ................................................................................................. 5-1 Tap Controller Public Instructions .............................................................................. 5-2 Tap Controller Private Instruction Codes.................................................................... 5-3 Test Mode State Selection ........................................................................................... 5-3 BIST Error Codes........................................................................................................ 5-5 Absolute Maximum Ratings ....................................................................................... 6-1 Recommended Operating Conditions ......................................................................... 6-2 DC Electrical Specifications ....................................................................................... 6-3 Transmitter DDR Timing Specification ...................................................................... 6-4 Transmitter SDR Timing Specification (LME = High, DDRE = Low)...................... 6-5 Receiver DDR Timing Specification .......................................................................... 6-5 Receiver SDR Timing Specification (LME = High, DDRE = Low) .......................... 6-6 Word Synchronization Bus Timing Specification....................................................... 6-7 Reference Clock Specification.................................................................................... 6-8 Recovered Clock Specification ................................................................................... 6-8 Link Differential Output Specification ....................................................................... 6-9 Link Differential Input Timing Specification ........................................................... 6-10 JTAG I/O Timing Specification ................................................................................ 6-11 Package Thermal Resistance Values ........................................................................... 7-5 324 MAPBGA Signal to Ball Mapping ...................................................................... 7-5 Components of a Character Name ..............................................................................B-2 Valid Data Characters..................................................................................................B-4 Valid Special Characters .............................................................................................B-8
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Tables
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Tables
Table Number Title Page Number
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About This Book
The primary objective of this user's manual is to describe the functionality of the MC92610 for software and hardware developers. Information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers' responsibility to be sure they are using the most recent version of the documentation.
Audience
It is assumed that the reader has the appropriate general knowledge regarding the design and layout requirements for high speed (Gbps) digital signaling and understanding of the basic principles of Ethernet and Fibre Channel communications protocols to use the information in this manual.
Organization
Following is a summary and a brief description of the major sections of this manual: * * * * Chapter 1, "Introduction," is useful for software and hardware engineers who need to have a general understanding of how the part works. Chapter 2, "Transmitter," describes the MC92610 transmitter, its interfaces and operation. Chapter 3, "Receiver," gives a description of the receiver. Chapter 4, "System Design Considerations," describes the system considerations for the MC92610, including clock configuration, device startup and initialization, and proper use repeater mode. Chapter 5, "Test Features," covers the JTAG implementation and the system accessible test modes. Chapter 6, "Electrical Specifications and Characteristics," describe the DC and AC electrical characteristics. Chapter 7, "Package Description," provides the package parameters and mechanical dimensions of the MC92610 device.
* * *
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About This Book
xiii
* * *
Appendix A, "Ordering Information," provides the Motorola part numbering nomenclature for the MC92610 transceiver Appendix B, "8B/10B Coding Scheme," provides fibre channel-specific 8B/10B encoding and decoding based on the ANSI FC-1 fibre channel standard. "Glossary of Terms and Abbreviations" contains an alphabetical list of terms, phrases, and abbreviations used in this book.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture and computer architecture in general: * The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, by International Business Machines, Inc. For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html. Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A. Patterson and John L. Hennessy
* *
Related Documentation
Motorola documentation is available from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: * User's manuals and reference manuals--These books provide details about individual device implementations. The MC92610DVB SERDES Design Verification Board Reference Manual (MC92610DVBRM/D) describes how to use the design verification board and should be read in conjunction with this manual, the MC92610 Quad 3.125 Gbaud SERDES User's Manual (MC92610UM/D). Addenda/errata to user's manuals--Because some devices have follow-on parts an addendum is provided that describes the additional features and functionality changes. These addenda are intended for use with the corresponding user's manuals. Hardware specifications--Hardware specifications provide specific data regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations. This manual contains all of the hardware specifications for the MC92610.
MC92610 SERDES User's Manual MOTOROLA
*
*
xiv
* *
*
Application notes--These short documents address specific design issues useful to programmers and engineers working with Motorola processors. White Paper-These documents provide detail on a specific design platform and are useful to programmers and engineers working on a specific product. MC92610 3.125 Gbaud Reference Design Platform (BR1570/D) describes the technical design process used in developing a high speed backplane. Additional literature is published as new processors become available. For a current list of documentation, refer to http://www.motorola.com/semiconductors.
Conventions
This document uses the following notational conventions: Book titles in text are set in italics Internal signals are set in italics, for example, qual BG 0x 0b x x n Prefix to denote hexadecimal number Prefix to denote binary number In some contexts, such as signal encodings, an un-italicized x indicates a don't care. An italicized x indicates an alphanumeric variable. An italicized n indicates an numeric variable.
Signals
A bar over a signal name indicate that the signal is active low--for example, XMIT_A_IDLE and XMIT_B_IDLE. Active low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as XMIT_EQ_EN and DROP_SYNC are referred to as asserted when they are high and negated when they are low.
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About This Book
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Chapter 1 Introduction
This user's manual explains the functionality of the MC92610 Quad 3.125 Gbaud SERDES transceiver and enable its use by software and hardware developers. The audience for this publication, therefore, consists of developers and application programmers who are building data path switches and applications.
1.1
Overview
The MC92610, is a high-speed, full-duplex, serial/deserializer (SERDES) data interface device that transmits data between chips across a board, through a backplane, or through cabling. The MC92610 has four transceivers that transmit and receive coded data at a maximum rate of 2.5 gigabits per second (Gbps) through each 3.125 gigabaud link. Each transceiver has redundant transmit and receive I/Os that are independently selectable. The MC92610 features HSTL class 1 DDR source synchronous parallel interfaces that allow efficient integration with system logic. The MC92610 is designed to minimize the number of data line interconnects in point-to-point communications with low power requirements. The MC92610 SERDES offers high performance with excellent signal integrity and low bit-error-rate (BER). Other features include clock generation and recovery, on-chip termination resistors and coupling capacitors, low transmit jitter, and multiple modes of operation - within a compact 324-pin MAPBGA package. The MC92610 features make it advantageous for use in many different data transfer designs. This in turn simplifies the architectures of switch backplanes while enabling small footprint designs. The MC92610 SERDES is the latest generation of Motorola's products. Like its predecessors, it features a very low power 0.25 CMOS implementation, using 1.8 Watts. with all links operating at full-speed. With a high-density packaging solution and a rich feature set the MC92610 is easily adaptable to many applications.
1.2
* *
Features
4 full-duplex differential data links. Selectable speed range: 3.125 Gbaud or 1.5625 Gbaud.
Chapter 1. Introduction 1-1
The following are the features of the MC92610:
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Block Diagram
* * * * *
*
* * * * * * * * * * *
Low power, nominally 1.8W, while operating all transceivers at full speed. Internal 8B/10B encoder / decoder that can be bypassed for applications where external coding is used. Double data rate (DDR), source synchronous, 8-bit and 10-bit HSTL class-1 parallel data interfaces. Received data may be clocked at the recovered clock or the reference clock frequency. Link-to-link synchronization supports aligned, 32-bit, word transfers. The synchronization mechanism can tolerates up to 40 bit-times of link-to-link media delay skew. Multi-chip link synchronization supports aligned, multi-word transfers. Up to four MC92610 devices may be used to provide 128-bit, four-word, synchronized transfers. Selectable Idle character alignment mode enables aligned transfers with automatic realignment or unaligned data transfers. Transceiver links operate over 50 media (100 differential) for lengths of up to one meter of FR-4 board/backplane or six meters of coax. Selectable transmit and receive link equalization. Link inputs have on-chip receiver termination, AC coupling and are "hot swap" compatible. Redundant transmitter outputs and receiver inputs are provided. Redundant links are selectable per transceiver. Broadcast mode enables all transmit link outputs. Differential reference clock input with single-ended reference clock input option. Link Multiplexer mode enables operation of two links with single data rate (SDR), source synchronous, 16-bit and 20-bit parallel data interfaces. Transceiver channels may be individually disabled. Repeater mode configures the MC92610 into a four-link receive-transmit repeater. At speed built-in self test (BIST) for in-system diagnostics. IEEE 1149.1 JTAG boundary scan test support.
1.3
Block Diagram
The MC92610 is a highly integrated device containing all of the logic needed to facilitate the application and test of a high-speed serial interface. A block diagram of the MC92610 device is shown in Figure 1-1.
1-2
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Block Diagram
XLINK_A0_N XLINK_A0_P XLINK_A1_N XLINK_A1_P RLINK_A1_P RLINK_A1_N RLINK_A0_P RLINK_A0_N
XMIT_A_CLK RECV_A[7:0], RECV_A_K, RECV_A_9, RECV_A_IDLE, RECV_A_ERR RECV_A_CLK XCVR_A_DISABLE, XCVR_A_RSEL
Transmit interface unit
Receive interface unit
Receiver
8B/10B decoder
Transmitter
XMIT_A[7:0], XMIT_A_K, XMIT_A_IDLE
8B/10B encoder
XMIT_B_CLK RECV_B[7:0], RECV_B_K, RECV_B_9, RECV_B_IDLE, RECV_B_ERR RECV_B_CLK XCVR_B_DISABLE, XCVR_B_RSEL CONFIG: TBIE, HSE, DDRE, LME, REPE, BSYNC, RCCE, ADIE, WSE, XMIT_EN_ALL, XMIT_REF_A, RECV_REF_A TEST: TST_0, TST_1, BIST_MODE_SEL, LBE, LBOE, SCAN_EN, TX_PLL_TPA DROP_SYNC, RESET WSI WSO TDO, TDI, TMS, TRST, TCK , TCK XMIT_C[7:0], XMIT_C_K, XMIT_C_IDLE XMIT_C_CLK RECV_C[7:0], RECV_C_K, RECV_C_9, RECV_C_IDLE, RECV_C_ERR RECV_C_CLK XCVR_C_DISABLE, XCVR_C_RSEL
Transmit interface unit
Transmitter
XMIT_B[7:0], XMIT_B_K, XMIT_B_IDLE
8B/10B encoder
XLINK_B0_N XLINK_B0_P XLINK_B1_N XLINK_B1_P RLINK_B1_P RLINK_B1_N RLINK_B0_P RLINK_B0_N
Receive interface unit
System integration unit
Receiver
8B/10B decoder
System PLL
REF_CLK_P REF_CLK_N
JTAG
RECV_EQ_EN, XMIT_EQ_EN Transmitter 8B/10B encoder XLINK_C0_N XLINK_C0_P XLINK_C1_N XLINK_C1_P RLINK_C1_P RLINK_C1_N RLINK_C0_P RLINK_C0_N
Transmit interface unit
Receive interface unit
Receiver
8B/10B decoder
XMIT_D_CLK RECV_D[7:0], RECV_D_K, RECV_D_9, RECV_D_IDLE, RECV_D_ERR RECV_D_CLK XCVR_D_DISABLE, XCVR_D_RSEL
Transmit interface unit
Transmitter
XMIT_D[7:0], XMIT_D_K, XMIT_D_IDLE
8B/10B encoder
XLINK_D0_N XLINK_D0_P XLINK_D1_N XLINK_D1_P RLINK_D1_P RLINK_D1_N RLINK_D0_P RLINK_D0_N
Receive interface unit
Figure 1-1. MC92610 Block Diagram
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Receiver
8B/10B decoder
References
1.4
[1] [2] [3]
References
Fibre Channel, Gigabit Communications and I/O for Computer Networks, Brenner, 1996. Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code, U.S. Patent #4,486,739, Dec. 4, 1984. High Speed Transceiver Logic (HSTL), A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, EIA/JEDIC Standard EIA/JESD8-6, Aug. 1995. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-1990 (Includes IEEE Std. 1149.1a-1993), Oct. 1993.
This section contains the indexed references in the document.
[4]
1.5
Revision History
Table 1-1. MC92610 SERDES User's Manual Revision History
Table 1-1 contains a brief description of the technical updates made to this document.
Revision Level 0 1
Change First revision of the MC92610 SERDES User's manual. Second revision of the MC92610 SERDES User's manual. Minor edits were made to the entire document. Added note in Section 5.1, "IEEE Std. 1149.1 Implementation," and Section 5.2.2, "BIST Sequence System Test Mode." Changed supply currents, power dissipation, min/max latencies in Chapter 6, "Electrical Specifications and Characteristics."
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Chapter 2 Transmitter
This chapter describes the MC92610 transmitter, its interfaces and operation. The chapter consists of the following sections: * * * Section 2.1, "Block Diagram" Section 2.2, "Transmitter Interface Signals" Section 2.3, "Functional Description."
The transmitter takes the data byte presented at its data input, creates a transmission character using its 8B/10B encoder (if not in 10-bit interface mode), and serially transmits the character out of the differential link output pads. A detailed explanation of the 8B/10B coding scheme is offered in Appendix B, "8B/10B Coding Scheme."
2.1
Block Diagram
Figure 2-1 shows a block diagram of the MC92610 transmitter.
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Chapter 2. Transmitter
2-1
Transmitter Interface Signals
.
XMIT_EQ_EN Serialization register XLINK_x0_P XMIT driver XLINK_x0_N TBIE LME DDRE REPE HSE XCVR_x_DISABLE XCVR_x_RSEL XMIT_EN_ALL TST_0 TST_1 LBE LBOE Input register Input register Transmitter controller 8B/10B encoder rx_clock loop_back_data XMIT driver XLINK_x1_N XLINK_x1_P
XMIT_REF_A XMIT_A_CLK XMIT_x_CLK XMIT_x_[7:0] XMIT_x_K XMIT_x_IDLE
BIST sequence generator
link_mux_data
repeat_data
Figure 2-1. MC92610 Transmitter Block Diagram
2.2
Transmitter Interface Signals
This section describes the interface signals of the MC92610 transmitters. Each signal is described, including its name, function, direction, and active state in Table 2-1. The table's signal names use the letter "x" as a place holder for the Link identifier letter "A" through "D". Internal signals are not available at the I/O of the device, but are presented to illustrate device operation.
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Transmitter Interface Signals
Table 2-1. MC92610 Transmitter Interface Signals
Signal Name XMIT_x_7 through XMIT_x_0 Description Transmit Byte Function Uncoded data/control byte to transmit. The least significant 8 bits of the pre-coded data transmits in TBI (ten bit interface) mode. Indicates that Transmit byte is a special control byte. Must be decoded with XMIT_x_IDLE to determine action, see Table 2-2. Pre-coded transmit data bit 8 in TBI mode. Transmit an Idle character. Must be decoded with XMIT_x_K to determine action, see Table 2-2. Pre-coded transmit data bit 9 in TBI mode. Direction Input Active State -
XMIT_x_K
Special Data Indicator
Input
High
XMIT_x_IDLE
Transmit Idle Character Bar
Input
Low
XMIT_x_CLK
Transmit Interface Clock Clock to which transmit interface signals are timed. Frequency requirement is dependent on whether HSE and DDRE are asserted. See Section 4.1 and Table 4-1 for configuration options. Transmit Interface Clock Indicates that the transmit interface Select signals are timed to XMIT_A_CLK instead of their transmit clock. Indicates that the transmitter and receiver for this transceiver are disabled. The link outputs are not driven. Indicates that the redundant link outputs are active and that the primary link outputs are disabled. The primary link outputs are active and the redundant link outputs are disabled when this signal is low. Both sets of outputs may be simultaneously enabled using the XMIT_EN_ALL signal. Indicates that both the primary and redundant link outputs are enabled independent of the assertion of the XCVR_x_RSEL signal. Broadcast mode does not override XCVR_x_DISABLE, which must be set low for transmitter operation. Indicates that transmitter equalization is enabled and that high frequency gain is applied to the transmitted signal.
Input
-
XMIT_REF_A
Input
High
XCVR_x_DISABLE Transceiver Disable
Input
High
XCVR_x_RSEL
Transceiver Link Select
Input
High
XMIT_EN_ALL
Transmitter Link Broadcast Enable
Input
High
XMIT_EQ_EN
Transmit Equalization Enable
Input
High
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2-3
Transmitter Interface Signals
Table 2-1. MC92610 Transmitter Interface Signals (continued)
Signal Name TBIE Description Function Direction Input Active State High
Ten-Bit Interface Enable Indicates that pre-coded 10-bit data is at inputs and to bypass internal 8B/10B coding. Repeater Mode Enable Link Multiplexer Mode Enable When enabled, the transmitter obtains transmit data from the receiver. Indicates that the data on transmitter A and B are aggregated and transmit out of link A. Likewise, the data on transmitter C and D are aggregated and transmit out of link C. When in Link Multiplexer mode (LME signal is high) this signal indicates that the data interfaces are running at double data rate. When not in Link Multiplexer mode, this signal does not affect device operation. When enabled, link is operated at half-speed. Both data and link interfaces run at half speed. Activate digital loopback path, such that data transmitted is looped back to its receiver. Indicates that selected link outputs remain active when loop back is enabled. The link outputs are disabled when LBOE is low and loop back is enabled. Selects a test mode. Differential serial transmit data output pads for the primary links. Differential serial transmit data output pads for the redundant links. Internal Signals
REPE LME
Input Input
High High
DDRE
Double Data Rate Enable
Input
High
HSE
Half Speed Enable
Input
High
LBE
Loop Back Enable
Input
High
LBOE
Loop Back Output Enable
Input
High
TST_1, TST_0 XLINK_x0_N/ XLINK_x0_P XLINK_x1_N/ XLINK_x1_P
Test Mode Select Link Serial Transmit Data, Primary Links Link Serial Transmit Data, Redundant Links
Input Output Output
-
rx_clock repeat_data link_mux_data
High Speed Transceiver Internal, differential high speed clock Clock used to transmit and receive link data. Received Repeat Data Link Multiplexer Mode Data Loop Back Data Repeater mode, received data to retransmit. Data from adjacent transmitter to transmit on this transmitter when in Link Multiplexer mode (LME is asserted.) Differential loop back transmit data.
Input Input Input
-
loop_back_data
Output
-
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Functional Description
2.3
Functional Description
The transmitter takes the data byte presented at its data input, creates a transmission character using its 8B/10B encoder and serially transmits the character out of the differential link output pads. The following sections provide a detailed description of the transmitter and its modes of operation.
2.3.1
Transmit Data Input Register Operation
The transmit data input register accepts data to be transmitted and synchronizes it to the internal clock domain. Transmit data is normally uncoded 8-bit data, however, transmission of pre-coded 10-bit data is supported in Ten-Bit Interface (TBI) mode. TBI mode is enabled by asserting TBIE high. The transmit data interface is a Double Data Rate (DDR) interface; the data is sampled and stored on the rising and falling edges of the transmit interface clock XMIT_x_CLK. There are several clocking options on the transmit data interface that are described in Section 2.3.1.5.
2.3.1.1
Transmitting Uncoded Data
Uncoded data is presented in 8-bit bytes to the input register through the XMIT_x_7- XMIT_x_0 signals. The uncoded data is coded into 10-bit transmission characters using an on-chip 8B/10B encoder. 8B/10B coding ensures DC balance across the link and sufficient transition density to facilitate reliable data recovery. The XMIT_x_7-XMIT_x_0 signals are interpreted as data when the XMIT_x_K signal is low. The 8B/10B code includes special control codes. Special control codes may be transmitted by asserting XMIT_x_K high, and XMIT_x_IDLE high as indicated in Table 2-2. The transmit byte is assumed to be a control code in this state. The transmitter generates an Idle character (K28.5) when XMIT_x_K is high and XMIT_x_IDLE is low as indicated in Table 2-2. An Idle character of proper running disparity is generated when this state is asserted; the state on the XMIT_x_7-XMIT_x_0 signals are ignored. This eases generation of Idle characters needed for byte and word synchronization and allows the link to maintain alignment when transmission of data is not needed.
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Functional Description
Table 2-2. Transmitter Control States
XMIT_x_IDLE -- Low High XMIT_x_K Low High High Description Transmit data present on XMIT_x_7-XMIT_x_0 inputs. Transmit Idle (K28.5), ignore XMIT_x_7-XMIT_x_0 inputs. Transmit control present on XMIT_x_7-XMIT_x_0 inputs.
2.3.1.2
Transmitting Pre-Coded Data
Ten-bit pre-coded data may be transmitted, bypassing the internal 8B/10B encoder. Ten-Bit Interface (TBI) mode is enabled by asserting TBIE high. In this mode, the ten bits to transmit are presented on the XMIT_x_7-XMIT_x_0 inputs, and bits 8 and 9 on the XMIT_x_K and XMIT_x_IDLE inputs, respectively. Precautions must be taken when using TBI mode. The 10-bit pre-coded data must exhibit the same properties as 8B/10B coded data. DC balance must be maintained and there must be sufficient transition density to ensure reliable data recovery at the receiver. The receiver requires that the K28.5 Idle character be periodically transmitted to enable byte and word synchronization. This 10-bit pattern, `0011111010' or `1100000101' (ordered from bit 0 through 9) is used for alignment and link-to-link synchronization when operating in any of the byte or word synchronization modes. The pattern of Idles and data required to achieve byte or word synchronization depends on the configuration of the receiver, see Section 3.3.4.3. The appropriate sequence must be applied through the Ten-Bit Interface. The MC92610 transmitter is comprised of several components whose operations are described in the following sections.
2.3.1.3
Link Multiplexer Mode
Link multiplexer mode configures the MC92610 quad device into a dual transceiver. The transmit data interfaces for transmitters A and B are combined to form a 16-bit/20-bit, Single Data Rate (SDR) interface. The data is sampled and stored on the rising edge of the transmit interface clock XMIT_A_CLK. The transmit data is aggregated and transmit out of link A. The outputs of link B are disabled. The transmit interface may also be operated in DDR mode by asserting DDRE high. Likewise, transmit data interfaces C and D are combined and transmit out of link C. Transmit interface clock XMIT_C_CLK is used for transmitters C and D. The outputs of link D are disabled.
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Functional Description
Data on the transmitter A interface is sent first, followed by transmitter B. Data on the transmitter C is sent first, followed by transmitter D. Link Multiplexer mode is enabled by asserting LME high.
2.3.1.4
Repeater Mode
Repeater mode configures the MC92610 into a 4-link receive-transmit repeater. In this mode, the data to transmit is obtained from its receiver (transmitter A gets receiver A's data, transmitter B gets receiver B's data, and so on). The transmit input signals, XMIT_x_7 XMIT_x_0, XMIT_x_K and XMIT_x_IDLE are ignored. Repeater mode is enabled by asserting REPE high. See Section 3.3.9 for more information on Repeater mode.
2.3.1.5
Transmit Interface Clock Configuration
The transmitter data interface operates at high frequency (up to 156.25MHz). In order to ease development of devices that interact with the MC92610, all of its data interfaces are source-synchronous. The data for each transmitter has its own dedicated clock input. This allows the clock at the source of the data to be routed with the data ensuring matched delay and timing. However, if per-transmitter clock sources are not available or deemed unnecessary, all transmitters may be clocked by a common clock source. This is enabled by asserting XMIT_REF_A high. When XMIT_REF_A is high, the XMIT_A_CLK becomes the interface clock for all active transmitters. The transmit interface clock inputs, XMIT_x_CLK, and the PLL reference clock, REF_CLK_P/REF_CLK_N, inputs must be operated at exactly the same frequency. However, there may be an arbitrary initial phase relationship between the PLL reference clock and the transmit interface clocks. The phase relationship between the transmit interface clock and the PLL reference clock is established after the internal PLL locks. Once locked, the transmit data interface tolerates +180o of transmit interface clock phase drift relative to the PLL reference clock. Additionally, all of the MC92610's data interfaces are DDR, except in Link Multiplexer mode. DDR interfaces, in which the data is sampled and stored on the rising and falling edges of the clock, reduces the clock frequency by 50 percent while maintaining throughput. The configuration assertings of the MC92610 affect the legal range of clock frequencies at which it may be operated. Section 4.1, Table 4-1 shows legal transmit interface clock frequencies for all modes of operation.
2.3.1.6
8B/10B Encoder Operation
The 8B/10B Encoder encodes 8-bit data/control from the input register into 10-bit transmission characters. The ANSI standard for Fibre Channel 8B/10B coding standard is followed [1,2]. Running disparity is maintained and the appropriate transmission characters
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Functional Description
are produced, maintaining DC balance and sufficient transition density to allow reliable data recovery at the receiver. The inputs to the 8B/10B Encoder are the data byte (XMIT_x_7-XMIT_x_0), special code signal (XMIT_x_K) and transmit Idle signal (XMIT_x_IDLE). Data and legal control bytes are coded according to the 8B/10B method. Illegal control bytes produce unpredictable transmission characters, leading to disparity and coding errors, ultimately reducing link reliability. The 8B/10B encoder produces an Idle character (K28.5) of proper running disparity when XMIT_x_IDLE is low and XMIT_x_K is high, as indicated in Table 2-2. The 8B/10B Encoder is bypassed in TBI mode.
2.3.1.7
Transmit Driver Operation
The Transmit Driver drives transmission characters serially across the link. There are two transmit drivers per transmitter, the primary driver for outputs XLINK_x0_P / XLINK_x0_N, and the redundant driver for outputs XLINK_x1_P / XLINK_x1_N. Each bit of coded data is transmitted differentially out of the enabled driver. The primary driver outputs, XLINK_x0_P / XLINK_x0_N, are enabled by asserting XCVR_x_RSEL low. The redundant driver outputs, XLINK_x1_P / XLINK_x1_N, are enabled by asserting XCVR_x_RSEL high. Broadcast mode is enabled by asserting XMIT_EN_ALL high. In broadcast mode, all primary and redundant link outputs of all four transmitters are enabled, independent of the asserting the XCVR_x_RSEL signals. When XMIT_EN_ALL is low, only the selected link driver is active as described previously. Both the primary and redundant link outputs are disabled when the transceiver is disabled by asserting XCVR_x_DISABLE high.
2.3.1.8
Transmit Equalization
The Transmit Driver is a 50 controlled impedance driver. The media over which the signals are transmit, has high-frequency loss that contributes significantly to a distortion known as Inter-Symbol Interference (ISI). In order to offset, or equalize, the loss at high frequency, the MC92610's Transmit Drivers provide additional gain at high frequencies. This is termed Transmit Equalization. Transmit equalization has the greatest benefit when driving longer lengths of coax or when traversing across a large backplane. Transmit equalization is of less benefit for short links. Transmit equalization is enabled by asserting XMIT_EQ_EN high.
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Functional Description
2.3.1.9
Loop-Back Test Mode
A special loop-back mode is supported for test. asserting LBE high enables loop-back mode causing the data being driven on the link outputs to be looped back to the input amplifier of the link's receiver. Loop-back data can be routed through either of the two output drivers. The path taken is controlled by the XCVR_x_RSEL signal. When XCVR_x_RSEL is low, data loops back through the primary driver (XLINK_x0_P / XLINK_x0_N), and when XCVR_x_RSEL is high, data loops back through the redundant driver (XLINK_x1_P / XLINK_x1_N). Loop-back data is processed the same as normally received data. Loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. The loop-back signals are electrically isolated from the link output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. When in loop-back mode, the LBOE signal controls the action of the link output signals. When LBOE is low, the link outputs are undriven and are high-impedance. When LBOE is high, the link output signals operate normally. LBOE has no affect on the operation of the device when LBE is low. See Section 5.2 for more information on system accessible test modes.
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Functional Description
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Chapter 3 Receiver
This chapter describes the MC92610 receiver, its interfaces and operation. This chapter has the following sections: * * * Section 3.1, "Receiver Block Diagram" Section 3.2, "Receiver Interface Signals" Section 3.3, "Receiver Functional Description"
The receiver takes a high speed differential serial data stream input, over samples it and recovers the data and clock, decodes it and presents it on a source synchronous parallel output data port.
3.1
Receiver Block Diagram
Figure 3-1 shows a block diagram of the MC92610 receiver.
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3-1
Receiver Interface Signals
loop_back_data RECV_EQ_EN RLINK_n0_P RECV Amp RLINK_n0_N RLINK_n1_P RECV Amp RLINK_n1_N LBE XCVR_n_RSEL BSYNC DROP_SYNC Idle Detection and Byte Alignment Transition Tracking Loop and Data Recovery Multi-Phase Sampler rx_clock
8B/10B Decoder
TBIE
WSE ADIE WSI WSO Word Alignment Alignment FIFO
REF_CLK_N/P recv_a_clk
XCVR_n_DISABLE Receive Controller BIST/BERT Analyzer link_mux_data
RCCE RECV_REF_A DDRE HSE
repeat_data RECV_n_[7:0] RECV_n_K RECV_n_9 RECV_n_IDLE RECV_n_ERR
Receiver Interface LME REPE TST_0 TST_1
RECV_n_CLK
Figure 3-1. MC92610 Receiver Block Diagram
3.2
Receiver Interface Signals
This sections describes the interface signals of the MC92610 receiver. Each signal is described, including its name, function, direction and active state in Table 3-1. The table's signal names use the letter "x" as a place holder for the Link identifier letter "A" through
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Receiver Interface Signals
"D." Internal signals are not available at the I/O of the device, but are presented to illustrate device operation.
Table 3-1. Receiver Interface Signals
Signal Name Description Function Received and decoded data/control byte. The least significant 8 bits of received data in TBI mode. Indicates that received byte is a special control byte. Received bit 8 in TBI mode. Errors are coded using this signal. See Section 3.3.6.3 for error codes. Received bit 9 in TBI mode. Unused in 8-bit mode. Indicates that the receiver detected an Idle character (operates in Byte and TBI modes). Errors are coded using this signal. See Section 3.3.6.3 for error codes. Indicates that the receiver detected an error. RECV_x_IDLE and RECV_x_K must be decoded to determine error condition. See Section 3.3.6.3 for error codes. Clock used for clocking receiver interface. Source and frequency of this clock depend on operating mode. See Section 4.1 for more information. Indicates that the current byte and word alignment should be invalidated and new alignment acquired. DROP_SYNC is level sensitive and not synchronized to a clock, it must be asserted for at least two clock periods. Indicates that the transmitter and receiver for this transceiver are disabled. Indicates that the redundant link inputs are observed and that primary link inputs are ignored. Indicates that receiver equalization is enabled and that high frequency gain is applied to the received signal. Direction Output Active State -
RECV_x_7 through Received Byte RECV_x_0
RECV_x_K
Special Data Indicator/ Received Bit 8
Output
-
RECV_x_9 RECV_x_IDLE
Received Bit 9 Receiver Idle Detect
Output Output
-
RECV_x_ERR
Receiver Error
Output
-
RECV_x_CLK
Receiver Interface Clock
Output
-
DROP_SYNC
Drop Synchronization
Input
High
XCVR_x_DISABLE Transceiver Disable XCVR_x_RSEL Transceiver Link Select
Input Input
High High
RECV_EQ_EN
Receive Equalization Enable
Input
High
TBIE
Ten-Bit Interface Enable Indicates that the receiver interface is in ten-bit mode and that the 8B/10B decoder is bypassed.
Input
High
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3-3
Receiver Interface Signals
Table 3-1. Receiver Interface Signals (continued)
Signal Name HSE Description Half Speed Enable Function Indicates to operate link at half-speed. Both data and link interfaces run at half speed. Activates digital loopback path, such that the loop-back data from the transmitter is accepted by the receiver. Indicates that all four receivers are being used in unison to receive synchronized data. Coded word synchronization bus input that is used to synchronize word timing between multiple MC92610 devices. See Section 3.3.4.3 for multi-chip word synchronization operation. This signal should be tied high if multi-chip word synchronization is not being used. Coded word synchronization bus output that is used to synchronize word timing between multiple MC92610 devices. See Section 3.3.4.3 for multi-chip word synchronization operation. Indicates that the data received on receiver A is presented 16/20 bits wide on parallel interfaces A and B. Likewise, the data received on receiver C is presented 16/20 bits wide on parallel interfaces C and D. When in Link Multiplexer Mode (LME is high) this signal indicates that the data interfaces are running at double data rate. Indicates that byte alignment is employed in the receiver. Indicates that the clock frequency recovered by the receiver is used for the receiver interface clock (RECV_x_CLK). Otherwise, the reference clock frequency is used. This signal is used with the RECV_REF_A signal to fully determine clock source. Direction Input Active State High
LBE
Loop Back Enable
Input
High
WSE
Word Synchronization Enable Word Synchronization Bus Input
Input
High
WSI
Input
-
WSO
Word Synchronization Bus Output
Output
-
LME
Link Multiplexer Mode Enable
Input
High
DDRE
Double Data Rate Enable
Input
High
BSYNC RCCE
Byte Alignment Mode Recovered Clock Enable
Input Input
High High
RECV_REF_A
Receiver Interface Clock Indicates that the clock frequency Select recovered by receiver A is used as the receiver interface clock for all four receivers. This signal is used with the RCCE signal to fully determine clock source.
Input
High
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Table 3-1. Receiver Interface Signals (continued)
Signal Name REF_CLK_P/N Description PLL Reference Clock Function PLL input reference clock. Provides reference frequency for the receiver interface when Recovered Clock mode is disabled (RCCE is low). Indicates that the receiver is free to add/delete Idle characters to/from the output data stream to maintain alignment. When enabled, the transmitter obtains transmit data from the receiver. Indicates operating/test mode of the chip. Direction Input Active State -
ADIE
Add/Delete Idle Enable
Input
High
REPE TST_0/ TST_1 RLINK_x0_N/ RLINK_x0_P RLINK_x1_N/ RLINK_x1_P
Repeater Mode Enable Test Mode
Input Input Input Input
High -
Link Serial Receive Data, Differential serial receive data input Primary Links pads for the primary links. Link Serial Receive Data, Differential serial receive data input Redundant Links pads for the redundant links. Internal Signals
rx_clock recv_a_clk loop_back_data link_mux_data
High Speed Transceiver Internal, differential high speed clock Clock used to transmit and receive link data. Receiver A Interface Clock Loop Back Data Link Multiplexer Mode Data Received Repeat Data Internal copy of receiver A's interface clock. Differential loop back receive data. Received data from adjacent receiver to direct to receiver interface when in Link Multiplexer mode (LME is high.) Repeater mode, received data to re-transmit.
Input Input Input Input
-
repeat_data
Output
-
3.3
Receiver Functional Description
The MC92610 receiver is based upon an oversampled transition tracking loop data recovery method. The receiver receives differential data in one of two operating ranges. It may be operated in full rate range with a maximum data rate of 2.5 Gbps (3.125 gigabaud) or at half-rate at 1.25 Gbps (1.5625 gigabaud). The operating range is determined by the state of the HSE input. The received serial data is accumulated into ten-bit characters. The ten-bit characters are forwarded to the 8B/10B decoder where the original data is obtained. Alternately, the decoder can be bypassed and the ten-bit character is forwarded to the receiver interface in ten-bit interface (TBI) mode.
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Receiver Functional Description
The receiver provides for byte (character) alignment. Alignment assures that the byte as presented at the input of the transmitter is preserved when the byte is presented by the receiver. Optionally, alignment may be disabled. The receiver also provides for word synchronization. In this mode, all of the receivers are being used cooperatively to receive 32-bit (40 bit in TBI mode) words. Word synchronization assures that the receivers present the four bytes of a word simultaneously. The MC92610 also supports multi-chip word synchronization in which up to four MC92610 devices may be used to send and receive synchronized multi-words. The receiver has primary and redundant link inputs to support applications where redundancy is required. MC92610's transition tracking loop has superior receive signal acquisition performance relative to PLL-based clock and data recovery methods. This enables faster transition between the primary and redundant data streams. The receiver interface, where the received bytes and status codes are obtained, has several modes of operation and timing to allow it to be used in a variety of applications. The following sections provide a detailed description of the receiver and its modes of operation.
3.3.1
Input Amplifier
The input amplifiers connect directly to the link input pads RLINK_x0_P/N and RLINK_x1_P/N. There are separate input amplifiers for the primary and redundant link inputs. The input amplifiers are differential with integrated analog multiplexer for loop-back testing. Differential 100 link termination and in-line AC coupling capacitors are integrated with the amplifiers. NOTE The integrated, in-line, AC coupling capacitors offer an extended common-mode input voltage range, however, compliance to the range as specified in Section 6.2 is required for proper link operation. If a broader common-mode input voltage range is required then additional, off-chip, AC coupling capacitors must be used. The input amplifier facilitates a loop-back path for production and in-system testing. When the MC92610 is in loop-back mode (LBE set high), the input amplifier selects the loop-back differential input signals and ignores the state on the RLINK_x0_P / RLINK_x1_P and RLINK_x0_N / RLINK_x1_N signals. Loop back data can be routed through either the primary or redundant input amplifier. The path taken is controlled by the XCVR_x_RSEL signal. When XCVR_x_RSEL is low, data loops back through the primary input amplifier, and when XCVR_x_RSEL is high, data loops back through the redundant input amplifier.
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Receiver Functional Description
Loop-back data is processed the same as normally received data. Loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. The loop-back signals are electrically isolated from the link input signals. Therefore, if the inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate normally. See Section 5.2 for more information on system accessible test modes.
3.3.1.1
Receiver Equalization
The media through which the signals are received, has high-frequency loss that contributes significantly to a distortion known as Inter-Symbol Interference (ISI). In order to offset, or equalize, the loss at high frequency, MC92610's input amplifiers provide additional gain at high frequencies. This is termed Receive Equalization. Receive equalization has the greatest benefit when receiving signals through longer lengths of coax or when traversing across a large backplane. Receive equalization is of less-benefit for short links. Receive equalization is enabled by asserting RECV_EQ_EN high. The input amplifier facilitates a loop-back path for production and in-system testing. When the MC92610 is in loop-back mode (LBE set high), the input amplifier selects the loop-back differential input signals and ignores the state on the RLINK_x0_P / RLINK_x1_P and RLINK_x0_N / RLINK_x1_N signals. Loop back data can be routed through either the primary or redundant input amplifier. The path taken is controlled by the XCVR_x_RSEL signal. When XCVR_x_RSEL is low, data loops back through the primary input amplifier, and when XCVR_x_RSEL is high, data loops back through the redundant input amplifier. Loop-back data is processed the same as normally received data. Loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. The loop-back signals are electrically isolated from the link input signals. Therefore, if the inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate normally. See Section 5.2 for more information on system accessible test modes.
3.3.1.2
Loop-Back Test Mode
The input amplifier facilitates a loop-back path for production and in-system testing. When the MC92610 is in loop-back mode (LBE set high), the input amplifier selects the loop-back differential input signals and ignores the state on the RLINK_x0_P / RLINK_x1_P and RLINK_x0_N / RLINK_x1_N signals. Loop back data can be routed through either the primary or redundant input amplifier. The path taken is controlled by the XCVR_x_RSEL signal. When XCVR_x_RSEL is low, data loops back through the primary input amplifier, and when XCVR_x_RSEL is high, data loops back through the redundant input amplifier.
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Receiver Functional Description
Loop-back data is processed the same as normally received data. Loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. The loop-back signals are electrically isolated from the link input signals. Therefore, if the inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate normally. See Section 5.2 for more information on system accessible test modes.
3.3.2
Transition Tracking Loop and Data Recovery
The received differential data from the input amplifier is sent to the transition tracking loop for data recovery. The MC92610 uses an oversampled transition tracking loop method for data recovery. The differentially received data is sampled and processed digitally providing for low bit error rate (better than 10-12) data recovery of a distorted bit stream. The transition tracking loop is tolerant of frequency offset between the transmitter and receiver. The MC92610 reliably operates with +100 ppm of frequency offset. The transition tracking loop synthesizes a recovered clock that matches the frequency of the received data. Recovered data is accumulated into 10-bit characters. Characters are aligned to their original 10-bit boundaries if a Byte Alignment mode is enabled.
3.3.3
Byte Alignment
The receiver supports the alignment of accumulated bits to their original transmitted character boundaries through Idle character recognition. Byte alignment is supported in Byte and TBI interface modes. Byte alignment is enabled by asserting BSYNC high.
3.3.3.1
Byte Alignment and Realignment Method
At power-up, the receiver starts an alignment procedure, searching for the 10-bit pattern defined by the 8B/10B Idle code. Alignment logic checks for the distinct Idle pattern, `0011111010' and `1100000101' (ordered bit 0 to bit 9), characteristic of the K28.5 Idle pattern. The search is done on the 10-bit data in the receiver, and is therefore independent being in Byte or TBI mode. Alignment requires a minimum of four, error-free, received Idle characters to ensure proper alignment and lock. Non-Idle characters may be interspersed with the Idle characters. The disparity of the Idle characters is not important to alignment and can be positive, negative or any combination. The receiver begins data flow of received characters once alignment is established and locked. However, if word synchronization is enabled, received characters do not flow to the receiver interface until word synchronization is established. Alignment remains locked until any one of three events occur that indicate loss of alignment: * Alignment is lost when a misaligned Idle sequence is detected. A misaligned Idle sequence is defined as four Idle characters with an alignment different than the
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Receiver Functional Description
*
*
current alignment. Non-Idle characters may be dispersed between the four misaligned Idles, however, a properly aligned Idle character breaks the sequence. Alignment is automatically changed to the newly detected alignment without halting data flow. Alignment is lost when the number of received characters with 8B/10B coding errors outnumbers the non-errored characters by four. Credit for non-errored characters in excess of errored characters is limited to four, such that alignment is lost after four consecutive errored characters. Misalignment detection of this type is not available in TBI mode. The receiver restarts its alignment procedure and halts data flow until a new alignment is established. Alignment is lost when the DROP_SYNC input is set high for at least two clock periods. Current alignment is invalidated, the receiver restarts its alignment procedure and halts data flow until a new alignment is established. DROP_SYNC is level-sensitive and asynchronous.
When establishing byte alignment, or when data flow is interrupted due to misalignment, the receiver's RECV_x_ERR signal is high and the "Not Byte Sync" error is reported as described in Section 3.3.6.3. NOTE During the power up sequence the receiver interface may have indeterminate data present and the RECV_x_CLK is disabled. When PLL lock is established the RECV_x_CLK becomes active and the receiver interface output data is forced to a negative running K28.5 character (0x17C on bits 9, k, data[7:0]) until a Byte-Sync is established.
3.3.3.2
Non-Aligned Method
No attempt is made to align the incoming data stream when BSYNC is low. The bits are simply accumulated into 10-bit characters and forwarded. This mode should be used only with TBI mode, TBIE set high, and with Word Synchronization disabled, WSE set low. At system reset and until the MC92610's system PLL is locked to its reference, the receiver's RECV_x_ERR signal is high and the "Not Byte Sync" error is reported, as described in Section 3.3.6.3. This may seem confusing because no byte synchronization is performed; but in this mode the status simply indicates that the system PLL has not achieved lock.
3.3.4
Word Synchronization
The four receivers in the MC92610 can be used cooperatively to receive 32-bit wide aligned word transfers. Word synchronization is enabled by asserting WSE high. Multiple
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Receiver Functional Description
MC92610 devices may be used to receive multi-word aligned transfers, through the use of the word synchronization bus interface. Word synchronization is possible in Byte or TBI mode. However, word synchronization is dependent on the detection of simultaneously transmitted word synchronization events that contain Idle characters. Therefore, if operating in TBI mode, the Idle character must be a supported member of the code set.
3.3.4.1
Word Synchronization Method
Word synchronization aligns characters in the receiver's alignment FIFO. Synchronization is accomplished by lining up word synchronization events detected by each of the receivers, such that all are coincident at the same stage of their FIFO. A word synchronization event is defined as four consecutive non-errored Idle (K28.5) characters followed by at least one non-Idle character. Word synchronization events must be generated at all concerned transmitters simultaneously in order for synchronization to be achieved. Word synchronization events must be received at all receivers within 40 bit-times of each other. Word synchronization is not attempted until all receivers are byte align locked. Word synchronization events are used to establish a relationship between the received bytes in each of the receivers. The bytes of a word are matched and presented simultaneously at the receiver interface. Once synchronization is achieved the receiver tolerates +6 bit-times of drift between receivers. If drift exceeds +6 bit-times the receiver will continue to operate. However, the received bytes will no longer be synchronized properly because the receiver remains locked on the initially established synchronization. Word synchronization remains locked until any one of the following three events occur that indicate loss of synchronization: Word synchronization lock is lost when one or more of the receivers lose or change byte alignment. Byte alignment loss is described in Section 3.3.3.1. Word synchronization lock is lost when overrun/underrun is detected on one or more of the receivers, see Section 3.3.6.3 for more about overrun/underrun. Word synchronization lock is lost when explicitly invalidated by asserting DROP_SYNC high for at least two clocks. When lock is lost, word synchronization must be re-established before data flow through the receiver resumes. The receiver interface is disabled during word synchronization. No data is produced at its outputs until word synchronization is achieved and the first non-Idle character is received. When establishing word synchronization, or when word synchronization is lost, the receiver's RECV_x_ERR signal is high and the "Not Word Sync" error is reported as described in Section 3.3.6.3.
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Receiver Functional Description
For further details on how the receiver interface is disabled during initial word synchronization see the note at the end of Section 3.3.3.1, "Byte Alignment and Realignment Method," on page 3-8.
3.3.4.2
Word Synchronization Bus
Word synchronization information and timing are communicated across the word synchronization bus. The WSO output drives the bus that is connected to the WSI inputs of other MC92610 devices with which word synchronization is desired. One of the MC92610 devices is connected as the Leader and the others as the Followers. The Leader's WSO output is used to drive its own WSI input and the WSI inputs of all of the Followers. The WSO output of the Follower devices is not used and is not connected. NOTE In order for word synchronization to operate properly in applications where only one MC92610 is used, the WSI input must be tied high.
3.3.4.3
Multi-Chip Word Synchronization
Up to four MC92610 devices may be connected to perform multi-word synchronized data transfer. Configurations of one, two, three and four devices are possible supporting 32-bit, 64-bit, 96-bit and 128-bit wide data transfers. One of the MC92610 devices is connected as the Leader and the others as the Followers as described in Section 3.3.4.2. Multi-chip word synchronization uses the same mechanisms for word synchronization as single-chip word synchronization as described in Section 3.3.4.1. Word synchronization events must be generated at all concerned transmitters simultaneously in order for synchronization to be achieved. Word synchronization events must be received at all receivers within 40 bit-times of each other. When the Leader device detects a word synchronization event at its receivers, it communicates the timing of the event to the Follower devices through the Word Synchronization Bus. The Follower devices use this timing to establish their own word synchronization relative to the Leader. Once synchronization is achieved, +6 bit-times of drift between all of the devices' receivers is tolerated. If drift exceeds +6 bit-times the devices will continue to operate. However, the devices will no longer be synchronized properly because they remain locked on the initially established synchronization. If any of the devices lose word synchronization, as described in Section 3.3.4.1, all of the receiving devices must be forced to lose synchronization to ensure proper resynchronization. Therefore, system logic should detect loss of word synchronization on all of the devices by decoding the "Not Word Sync" error. Then the DROP_SYNC should
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Receiver Functional Description
be set high for at least two clock cycles and then released to force all devices to re-establish word synchronization.
3.3.4.4
Recommended Mode States for Word Synchronization
Word synchronization can only be used with certain operating modes and has limited application in others. Table 3-2 describes the relationship between modes and word synchronization.
Table 3-2. Word Synchronization States
Mode Word Synchronization Byte Synchronization Signals WSE BSYNC Recommended State High High Description Enables word synchronization. Word synchronization depends upon Idle character detection. Byte alignment is required for Idle detection. When enabled, allows the receiver to add/delete Idle patterns in order to maintain word alignment. This is the recommended operating mode when the Reference Clock is being used to time the receiver interface (RCCE set low) and there is a frequency offset between the transmitter and receiver. Idles are added or dropped to maintain word alignment. The receiver interface must be timed with the Reference Clock when utilizing multi-chip word synchronization. Timing errors will occur on the word synchronization bus if RCCE is high. If utilizing single chip word synchronization, then either the Recovered Clock or the Reference Clock may be used to time the receiver interface. RCCE may be set as it best suites the application. If utilizing single chip word synchronization and using the Recovered Clock (RCCE set high) then receiver A's recovered clock must be used for all receivers. The data at the receiver interfaces will be skewed if the individual receiver recovered clocks (RECV_REF_A set low) are used to time the receiver interfaces. All four transceivers must be enabled for word synchronization. Word synchronization is not recommended in Repeater mode. When enabled, the Idle character must be part of the TBI code set. When disabled, the Idle is naturally supported by the 8B/10B codes. Word synchronization operates normally in Link Multiplexer mode.
Add/Delete Idle
ADIE
High
Recovered Clock
RCCE
Low
Receiver Interface Clock Select
RECV_REF_A
High
Transceiver Disable Repeater Mode Ten-Bit Interface
XCVR_x_DISABLE REPE TBIE
Low Low n/a
Link Multiplexer Mode
LME
n/a
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Receiver Functional Description
Table 3-2. Word Synchronization States (continued)
Mode Half-Speed Enable Double Data Rate Signals HSE DDRE Recommended State n/a n/a Description Does not affect word synchronization. Does not affect word synchronization.
3.3.5
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the Transition Tracking Loop and decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of error checking. First it checks that all characters are a legal member of the 8B/10B coding space. The decoder also checks for running disparity errors. If the running disparity exceeds the limits set in the 8B/10B coding standard then a disparity error is generated. NOTE 8B/10B coding is meant only to improve data transmission characteristics and is not a good error detection code. Many 8B/10B characters alias to other valid 8B/10B characters in the presence of bit errors. Error detection and correction techniques must be applied outside of MC92610 if better than 10-12 bit error rate is required. An illegal character or disparity error sets the RECV_x_ERR signal high, coincident with the received data for one byte output period. The "Code Error" or "Disparity Error" is reported as described in Section 3.3.6.3. It is difficult to determine the exact byte that causes a disparity error, so the error should not be associated with a particular received byte. It is rather a general indicator of the improper operation of the link. Its intended use is for the system to monitor link reliability. The 8B/10B decoder is bypassed when operating in TBI mode (TBIE set high.)
3.3.6
Receiver Interface
The receiver interface facilitates transfer of received data to the system. It also provides information on the status of the link. Table 3-1 describes each of the signals involved in receiver operation. The receiver interface, through which received data is obtained, may be operated in Byte mode or in TBI mode. There are several timing mode options for the receiver interface. Each of the operating modes are described below.
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Receiver Functional Description
3.3.6.1
Byte Interface
Byte interface mode is enabled by setting TBIE low. Received data is a byte (8 bits) of uncoded data when in Byte mode. The internal 8B/10B decoder is used to decode data from the 10-bit character received. The received byte is on the RECV_x_7-RECV_x_0 signals. The RECV_x_K is high when the byte represents a special 8B/10B code, otherwise it is low, indicating that the byte is normal data. The RECV_x_IDLE is high when the byte is the special 8B/10B Idle (K28.5) code. This can be used by system logic for synchronization or data parsing. RECV_x_IDLE is low when the byte is normal data or a non-Idle special code. RECV_x_IDLE is high and RECV_x_K is low to indicate that an underrun/overrun error occurred. See Section 3.3.6.3 for more information on error conditions. The RECV_x_ERR is low when the receiver is operating normally, and is high when received data contains an error or the receiver is in an error state. The state of the RECV_x_IDLE and RECV_x_K signals are decoded to determine the error condition. Table 3-3 describes the error codes and their meaning.
3.3.6.2
Ten-Bit Interface
Ten-Bit Interface mode is enabled by setting TBIE high. Received data is ten-bits of pre-coded data when in TBI mode. The internal 8B/10B decoder is not used and it is assumed that decoding is done externally. Ten-bit data is the collection of signals: RECV_x_9, RECV_x_K, and RECV_x_7-RECV_x_0 making up bits 9 through 0, respectively. The RECV_x_IDLE is high when the 10-bit character is the special 8B/10B Idle (K28.5) code. This can be used by system logic for synchronization or data parsing. RECV_x_IDLE is low when the data is normal data or a non-Idle special code. The RECV_x_ERR is low when the receiver is operating normally, and is high when the receiver is in an error state. The state of the RECV_x_IDLE signal is decoded to determine the error condition. Table 3-4 describes the error codes and their meaning.
3.3.6.3
Receiver Interface Error Codes
The receiver's status and data error conditions are coded on the RECV_x_ERR, RECV_x_IDLE and RECV_x_K signals. When RECV_x_ERR is low, the receiver is operating normally and no error conditions exist (with exception of Underrun/overrun error in Byte mode.) When RECV_x_ERR is high, the data on the receiver's output is questionable due to an error condition or lack of synchronization. Initially, RECV_x_ERR is high indicating that the receiver is in one of its start-up phases. Table 3-3 describes the error conditions and their signal coding for Byte mode. Table 3-4 describes the error conditions and their signal coding for TBI mode. The Priority column in the tables show
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Receiver Functional Description
the error reported if multiple errors occur at the same time. The lower the Priority numbered errors are reported first.
Table 3-3. Receiver Interface Error Codes (Byte Interface)
RECV_x_ERR RECV_x_K RECV_x_IDLE Priority Low Low Low Low Low High 8 3 Description Normal operation, valid data character received. Overrun / Underrun: The receiver interface synchronization logic detected an overrun/underrun condition. Data may be dropped or repeated. Normal operation, valid control character received. Normal operation, valid Idle (K28.5) character received. Code Error: The 8B/10B decoder detected an illegal character. Disparity Error: The 8B/10B decoder detected a disparity error. Not Byte Sync: The receiver is in start-up or has lost byte alignment and is searching for alignment. Not Word Sync: The receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment.
Low Low High High High High
High High Low Low High High
Low High Low High Low High
7 6 4 5 1 2
Table 3-4. Receiver Interface Error Codes (Ten-Bit Interface)
RECV_x_ERR RECV_x_IDLE Low Low High High Low High Low High Priority 4 3 1 2 Description Normal operation, non-Idle character received. Normal operation, Idle (K28.5) character received. Not Byte/Word Sync: The receiver is in start-up or has lost byte or word alignment and is searching for alignment. Overrun/Underrun: The receiver interface synchronization logic detected and overrun/underrun condition. Data may be dropped or repeated.
3.3.7
Receiver Interface Clock Timing Modes
The receiver interface is double data rate, source synchronous. Each of the receiver's eleven output signals (eleven for byte interface and twelve for ten-bit interface) are timed relative to the rising and falling edges of the receiver interface clock output, RECV_x_CLK. The receiver interface clock frequency may be selected between its own recovered clock frequency, receiver A's recovered clock frequency, or the frequency of the reference clock input(s) REF_CLK_P / REF_CLK_N. The recovered clock enable signal, RCCE, determines if the receiver interface is timed to the recovered clock or to the local reference clock. Asserting RCCE enables timing relative to the recovered clock, and set low enables timing relative to the reference clock. When
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Receiver Functional Description
RCCE is asserted high, then the signal RECV_REF_A is used to select the recovered clock to be used. If RECV_REF_A is asserted then Channel A's recovered clock is used for all four channels. If it is low then each channel uses its own recovered clock. The receiver interface clock signals, RECV_x_CLK, will always be present when the PLL is in lock. This is true even if there is no signal present on the serial inputs or if the receiver has not achieved alignment or byte sync. The frequency of the receiver clock will be the local reference clock. The clock signals however, are not present during power up or when the MC92610 is in reset mode and the PLL is not locked.
3.3.7.1Recovered Clock Timing Mode
With RCCE asserted, the recovered clock signal, RECV_x_CLK, is generated by the receiver and, on average, runs at the reference clock frequency of the transmitter at the other end of the link. The recovered clock is not generated by a clock recovery PLL, but is generated by the receiver bit-accumulation and byte-alignment logic. In order to track a transmitter frequency that is offset from the receiver's reference clock frequency, the duty cycle and period of the recovered clock is modulated. The MC92610 is designed to tolerate up to a 200 ppm of frequency offset. The recovered clock duty cycle may be reduced or increased (by 200 ps, if the nominal frequency is 156.25 Mhz) in order to match the transmitter frequency. For example: If the transmitter is sending data at a rate faster than the receiver, then a shortened cycle is generated as needed to track the incoming data rate. Alternately, if the transmitter is running slower than the receiver, then a long cycle is generated. All receiver channel outputs are source synchronous with their respective RECV_x_CLK outputs. If the receivers are being operated in word synchronization mode (WSE = high), the data for all four receivers are timed relative to link A's recovered clock RECV_A_CLK. In word synchronization all four clocks are derived from channel A and may be used if necessary.
3.3.7.2
Reference Clock Timing Mode
Data is timed relative to the local reference clock frequency when RCCE is low. Synchronization between the recovered clock and the reference clock is handled by the receiver interface. Frequency offset between the transmitter's reference clock and the receiver's reference clock causes overrun/underrun situations. Overrun occurs when the transmitter is running faster than the receiver. Underrun occurs when the transmitter is running slower than the receiver. In an overrun situation, a byte of data needs to be dropped in order to maintain synchronization between the clock domains. The receiver interface searches for an Idle byte to drop when overrun is imminent. However, the Idle is dropped only if Add/Delete Idle (ADI) mode is enabled by asserting ADIE. When enabled, Idle patterns are dropped to
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Receiver Functional Description
maintain synchronization. If sufficient Idle patterns are not available to drop, receiver overrun may occur. When overrun occurs, the "overrun/underrun" error is reported as described in Section 3.3.6.3, "Receiver Interface Error Codes," for one byte clock period. An overrun error is also reported if ADI mode is disabled and overrun occurs, even if Idles are available to drop. A sufficient number of Idles must be transmitted to guard against overrun. The frequency of Idles can be computed based upon the maximum frequency offset between transmitter and receiver in the system. The number of bytes (characters) that can be transmitted between Idles is: (106 / N) - 1 bytes where: N is the frequency offset in ppm. In an underrun situation, a byte of data needs to be added in order to maintain synchronization between the clock domains. The receiver interface adds an Idle byte when underrun is imminent. However, the Idle is added only if Add/Delete Idle (ADI) mode is enabled by asserting ADIE. If ADI mode is disabled and underrun occurs, the "overrun/ underrun" error is reported as described in Section 3.3.6.3, "Receiver Interface Error Codes," for a one byte clock period.
3.3.8
Half-Speed Mode
Half speed (HS) mode, enabled when HSE is high, operates the receiver in its lower speed range. In HS mode, the link speed is 1.25 Gbps (1.5625 gigabaud.) The receiver interface operates at half speed as well, in pace with received data.
3.3.9
Repeater Mode
Repeater mode configures the MC92610 quad device into a 4-link receive-transmit repeater. In this mode, received data is forwarded to the transmitter for re-transmission. Link A's receiver forwards to Link A's transmitter, Link B's receiver to Link B's transmitter and so on. The receiver's data outputs and status signals reflect the received data and the current status of the receiver. See Section 2.3.1.4 for more information on repeater mode.
3.3.10 Link Multiplexer Mode
Link multiplexer mode configures the MC92610 quad device into a dual transceiver. The Link multiplexer mode is enabled by asserting LME high. Receivers A and C are active and are used to receive data. The input circuitry to receivers B and D are disabled and inactive. The advantage of this mode is that data from a single receiver is demultiplexed onto two receiver interfaces. Their single data rate (SDR) operation allows full speed link operation while lowering the parallel interface speeds by one-half. Data from receiver A is presented on receiver interfaces A and B. Once byte synchronization is achieved, the first non-Idle character received is output on receiver
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Receiver Functional Description
interface A, the second on receiver interface B. It is recommended that Idles be transmitted simultaneously as A and B pairs. If Idles are transmitted on only one input byte, they must be on B to maintain the proper byte order in the 16 bit output. The link status codes on receiver interface A and B represent the status of the current character. Both sets of status signals are active and must be observed. The received data is timed relative to the rising edge of the receiver interface clock, RECV_x_CLK. The receive interface may also be operated in DDR mode by asserting DDRE high. Link Multiplexer mode is enabled by asserting LME high.
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Chapter 4 System Design Considerations
This chapter describes the system design considerations for the MC92610, including clock configuration, device startup and initialization, and proper use of repeater mode.
4.1
Reference Clock Configuration
The clock inputs REF_CLK_P and REF_CLK_N are the differential reference clock inputs for the MC92610. The frequency of the clock signal applied to these inputs along with the settings on the configuration inputs determine the speed at which the serial links operate. Also, the legal ranges of reference clock frequencies vary depending on the configuration selected. Table 4-1 shows the ranges allowed for each configuration.
Table 4-1. Legal Reference Clock Frequency Ranges
HSE LME DDRE Reference Frequency Min (MHz) reserved 95.00 95.00 47.50 reserved 47.50 47.50 23.75 Reference Frequency Max (MHz) reserved 156.25 156.25 78.125 reserved 78.125 78.125 39.0625 Link Transfer Rate (Gigabaud) reserved 1.900 - 3.125 1.900 - 3.125 1.900 - 3.125 reserved 0.950 - 1.5625 0.950 - 1.5625 0.950 - 1.5625
Low Low Low Low High High High High
Low Low High High Low Low High High
Low High Low High Low High Low High
NOTE The device must be reset by setting RESET low, if the reference clock configuration is changed after power-up. The clock inputs REF_CLK_P and REF_CLK_N are normally driven with a differential clock source. However, the reference clock may also be driven with a single-ended source. In this situation, the REF_CLK_P signal is driven by the single-ended clock source and the REF_CLK_N signal is held at the HSTL reference voltage as defined in Section 6.2. The
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Startup
REF_CLK_N signal may be connected to its own reference voltage circuit or may share the reference voltage circuit used for the HSTL_VREF signal, if board layout allows.
4.2
Startup
The MC92610 begins a startup sequence upon application of the reference clock (REF_CLK_N/P input) to the device. This is considered a cold startup. The cold startup sequence is as follows: 1. 2. 3. 4. PLL Startup Receiver Initialization and Byte Alignment Word Alignment (if enabled) Run
The expected duration of each step in the startup sequence is shown in Table 4-2. A cold startup can be initiated at any time by setting RESET low. It is recommended that RESET be low at initial startup, however, it is not strictly required.
Table 4-2. Startup Sequence Step Duration
Startup Step PLL Startup Receiver Initialization Typical Duration (in bit times) 20,480 + 25 s 300 460 Word Alignment 160 WSE = low WSE = high Note
4.3
Repeater Mode
The MC92610 may be configured into a four-link receive-transmit repeater by setting REPE high. In repeater mode data received on link A's receiver is forwarded to link A's transmitter, link B's receiver to link B's transmitter and so on. The configuration inputs may be used to control how the repeater handles the data as it passes through the repeater. Certain configurations are more effective than others for various applications. The transmitter at the source, the receiver at the destination and the repeater must have compatible configurations to ensure proper operation. The following sections describe how each configuration control affects repeater operation.
4.3.1
Ten-Bit Interface Mode
When the device is in TBI mode (TBIE set high) the internal 8B/10B encoder and decoder are bypassed and the ten-bit data received is forwarded directly to the transmitter. Running disparity is assumed correct and is not checked. This is important when using disparity based word synchronization where incorrect running disparity is used as a word
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Repeater Mode
synchronization event marker. Ten-bit mode must be enabled for disparity based word alignment to operate properly because it allows the improper disparity to pass through the repeater. When Byte interface mode is enabled (TBIE set low) received data is passed through the 8B/10B decoder where it is converted into its eight-bit data or control byte. Running disparity and code validity are checked and reported with the received byte at the receiver interface as described in Section 3.3. The decoded byte is re-coded by the transmitter's 8B/10B encoder for transmission. NOTE Byte Interface mode must not be used with Non-Aligned mode.
4.3.2
Byte Alignment Mode
The Byte Alignment may be used in repeater mode as long as Ten-Bit Interface mode is not also being used. When establishing byte alignment for the link through the repeater, the byte alignment sequence must be repeated twice, once for the repeater and once for the destination's receiver. For example, at least eight Idle characters must be transmit, four for repeater alignment and four for the destination's receiver alignment.
4.3.3
Word Synchronization Mode
Word synchronization may be used in Repeater mode. This allows the incoming bytes to be synchronized into their corresponding words, removing cable skew from the transmission source and re-establishing synchronization. Similar to Byte Alignment, the Word Synchronization sequence must be repeated twice, once for the repeater and once for destination's receiver. For example, a 4 Idle/1 non-Idle word synchronization event must be transmit followed by a second 4 Idle/1 non-Idle word synchronization event to enable the entire link to establish word synchronization. Of course, byte alignment must be established, as described in Section 4.3.2, prior to word synchronization.
4.3.4
Recovered Clock Timing Mode
The MC92610's four transmitters are timed exclusively to the Reference Clock domain. Recovered Clock mode cannot be used in Repeater mode. The setting on the Recovered Clock Enable input, RCCE, is ignored when in Repeater mode and all data is timed to the Reference Clock.
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Configuration and Control Signals
4.3.5
Reference Clock Timing Mode
Repeater mode is timed exclusively to the reference clock domain as stated above. A frequency offset between the source transmitter and the repeater will cause the repeater's receiver to eventually overrun/underrun. To ensure that overrun/underrun does not cause data to be lost, add/drop idle mode must be used. Add/drop idle mode is enabled by setting ADIE high. The repeater adds or drops Idles from the data stream to maintain alignment to the reference clock. The guidelines for Idle density are discussed in Section 4.3.2.
4.3.6
Half-Speed Mode, Double Data Rate Mode
Half-speed mode and double data rate mode simply affect the frequency of the reference clock that must be provided and the timing of the receiver interface. All combinations of these modes are supported in repeater mode. See Section 3.3.8 for more information on half-speed mode and Section 3.3.6 for more information on double data rate mode.
4.4
Configuration and Control Signals
MC92610 has many configuration and control signals that are asynchronous to all inputs clocks. Most of the signals affect internal configuration state and must be set at power-up. If their state is changed after power-up, some require that the chip be reset by setting RESET_B low and then releasing high. While other configuration signals are meant to be changed during normal operation and do not require chip reset. However, these signals may still affect device operation. Table 4-3 lists all of the MC92610's asynchronous configuration and control signals and describes the effect of changing their state after power up.
Table 4-3. Asynchronous Configuration and Control Signals
Signal Name XCVR_x_RSEL Description Transceiver Redundant Link Select Effect of Changed State Receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. Receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. Receiver must re-establish byte and word synchronization. Device must be reset. Device must be reset. May cause short burst of bit errors. May cause short burst of bit errors. No action required.
XCVR_x_DISABLE
Transceiver Disable
DROP_SYNC XMIT_REF_A RECV_REF_A XMIT_EQ_EN RECV_EQ_EN XMIT_EN_ALL
Drop Synchronization Transmitter Reference Clock A Select Receiver Reference Clock A Select Transmitter Equalization Enable Receiver Equalization Enable Transmitter Enable, All Outputs
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Table 4-3. Asynchronous Configuration and Control Signals (continued)
Signal Name TBIE HSE DDRE BSYNC ADIE REPE LME RCCE WSE LBE Description Ten-Bit Interface Enable Half-Speed Enable Double Data Rate Enable Byte Synchronization Mode Add/Drop Idle Enable Repeater Mode Enable Link Multiplexer Mode Recovered Clock Enable Word Synchronization Enable Loop Back Enable Effect of Changed State Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. No action required. Device is reset.
LBOE RESET
Loop Back Output Enable System Reset Bar
4.5
Power Supply Requirements
The recommended board for the MC92610 has a minimum of two solid planes of one ounce copper. One plane is to be used as a ground plane and the second plane is to be used for the 1.8V supply. It is recommended that the board has its own 1.8V and 1.5V regulators with less than 50mV ripple.
4.6
Phase Locked Loop (PLL) Power Supply Filtering
An analog power supply is required. The TX_PLLVDD signal provides power for the analog portions of the PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 4-1. For maximum effectiveness, the filter circuit is placed as close as possible to the TX_PLLVDD ball to ensure it filters out as much noise as possible. The ground connection should be near the TX_PLLVDD ball. The 0.003mF capacitor is closest to the ball, followed by the 1 mF capacitor, and finally the 1 W resistor to Vdd on the 1.8V power plane. The capacitors are connected from TX_PLLVDD to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct.
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Power Supply Decoupling Recommendations
1 VDD 1.0 F 0.003 F TX_PLLVDD
GND
Figure 4-1. PLL Power Supply Filter Circuits
4.7
Power Supply Decoupling Recommendations
The MC92610 requires a clean, tightly regulated source of power to ensure low jitter on transmit, and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used, to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. First, the board should have about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 1.8v (Vdd and XVdd) balls of the device. The board should also have about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 1.5v (VDDQ) balls of the device. Where the board has blind vias, these capacitors should be placed directly below the MC92610 supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the MC92610, as close to the supply and ground connections as possible. Second, there should be a 1uF ceramic chip capacitor on each side of the MC92610 device. This should be done for both the 1.8v supply and the 1.5v supply. Third, between the MC92610 device and the voltage regulator, there should be a 10uF, low equivalent series resistance (ESR) SMT tantalum chip capacitor, and a 100uF, low ESR SMT tantalum chip capacitor. This should be done for both the 1.8v supply and the 1.5v supply.
4.8
HSTL Reference Voltage Recommendation
The MC92610 uses HSTL Class-I inputs and outputs for all of its high-frequency parallel interface signals. The HSTL Class-I interfaces are compatible with the EIA/JEDEC standard EIA/JESD8-6 [3]. HSTL Class-I inputs define their switching thresholds about a reference voltage supplied at an input of the device. The reference voltage is applied to the HSTL_VREF input of the MC92610. The reference voltage, referred to as VREF in Table 6-3, must fall within the
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Impedance Control Reference Recommendation
minimum and maximum voltages as specified and must have no more than 2 percent peak-to-peak AC noise. In practice, VREF for the HSTL inputs should track the variations in the DC value of VDDQ of the sending device for best noise margin. The value of VREF is to be selected by the user to provide optimum noise margin. Figure 4-2 shows a recommended circuit topology to generate VREF with recommended ceramic chip filter capacitor.
VDDQ
100 HSTL_VREF 110 1.0 F
GND
GND
Figure 4-2. HSTL Class-I VREF Circuit
4.8.1
Voltage Reference for Single-Ended Reference Clock Use
The differential reference clock inputs, REF_CLK_P/N, may also be driven by a single-ended source as described in Section 4.1. The REF_CLK_N input must be set at VREF for single-ended operation of REF_CLK_P. The REF_CLK_N signal may be connected to its own reference voltage circuit or may share the reference voltage circuit used for the HSTL_VREF signal, if board layout allows.
4.9
Impedance Control Reference Recommendation
The MC92610 has an integrated active impedance calibration circuit to ensure the best possible impedance control of the receiver's link termination resistors. The calibration circuit uses an externally established impedance against which internal impedance is calibrated. The user connects a 250 , 1percent tolerance, resistor between the MC92610 Z_CALIB input and ground. The Z_CALIB input may be tied to GND to disable impedance calibration, or may be tied to VDD which will set the input impedance to its maximum value. Figure 4-3 shows an example impedance reference circuit topology.
MOTOROLA
Chapter 4. System Design Considerations
4-7
Impedance Control Reference Recommendation
Z_CALIB 250
GND
Figure 4-3. Impedance Reference Circuit
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Chapter 5 Test Features
The MC92610 supports several test modes for in-system BIST and production testing. The MC92610 also has an IEEE Std. 1149.1 [4] compliant Test Access Port and Boundary Scan Architecture implementations. This chapter covers the JTAG implementation and the system accessible test modes.
5.1
IEEE Std. 1149.1 Implementation
This section describes the IEEE Std. 1149.1 compliant Test Access Port and Boundary Scan Architecture implementation in the MC92610. NOTE There are no internal pull-ups/pull-downs on any JTAG input. This is an exception to the IEEE Std. 1149.1 standard. The inputs should be properly terminated externally.
5.1.1
Test Access Port (TAP) Interface Signals
Table 5-1. TAP Interface Signals
Table 5-1 lists the interface signals for the TAP.
Signal Name TCK TMS TDI TRST TDO
Description Test Clock Test Mode Select Test Data In Test Reset Bar Test Data Out
Function Test logic clock. TAP mode control input. Serial test instruction/data input. Asynchronous test controller reset. Serial test instruction/data output.
Direction Input Input Input Input Output
Active State Low -
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Chapter 5. Test Features
5-1
IEEE Std. 1149.1 Implementation
NOTE If TRST is not held low during power-up or does not receive an active low reset after power-up, the test logic may assume an indeterminate state disabling some of the normal transceiver functions. It is recommended that TRST be terminated in one of the following manners. 1. TRST be driven by a TAP controller that provides a reset after power-up. 2. Connect TRST to RESET. 3. Terminate TRST with a 1K Ohm resistor (or hard wire) to ground.
5.1.2
Is the
Instruction Register
Bit Position Field Capture-IR Value 0 0
4 3 2 1 0
IR 0 0 1
Figure 5-1. Instruction Register
5.1.3
Instructions
Table 5-2 lists the Public instructions provided in the implementation and their instruction codes.
Table 5-2. Tap Controller Public Instructions
Instruction BYPASS CLAMP EXTEST HIGHZ IDCODE SAMPLE Code 11111 01100 00000 01001 00001 00010 Bypass Register Bypass Register Boundary Scan Register Bypass Register ID Register Boundary Scan Register Enabled Serial Test Data Path
Table 5-3 lists the Private instruction codes that if executed could be hazardous to device operation. The user should not execute these instructions.
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System Accessible Test Modes
Table 5-3. Tap Controller Private Instruction Codes
Instruction Code 10000 10010 10100 10110 11000 11010 11100 11110 Instruction Code 10001 10011 10101 10111 11001 11011 11101 -
5.1.4
Boundary-Scan Register
A full description of the boundary scan register may be found in the BSDL file provided by Motorola upon request.
5.1.5
31
Device Identification Register (0x0280E01D)
28 27 12 11 0
Field VERSION
PART NUMBER
MANUFACTURER ID
Value 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1
Figure 5-2. Device Identification Register
5.1.6
Performance
The performance and electrical properties of the tap controller, boundary scan, and JTAG inputs and outputs are described in Chapter 6, "Electrical Specifications and Characteristics.
5.2
System Accessible Test Modes
System accessible test modes are selected through the TST_0, TST_1 and LBE signals. Table 5-4 shows test mode state selection.
.
Table 5-4. Test Mode State Selection
TST_1 Low Low Low TST_0 Low Low High LBE Low High Low Description Normal operation. No test mode enabled. Loop back system test mode. BIST sequence system test mode.
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Chapter 5. Test Features
5-3
System Accessible Test Modes
Table 5-4. Test Mode State Selection
TST_1 Low High TST_0 High Don't care LBE High Don't care Description Loop back BIST sequence system test mode. Reserved.
5.2.1
Loop Back System Test
The MC92610 can be configured in loop back mode where the transmitted data is looped back to its receiver independent of the receiver's link inputs. This is enabled by setting LBE high. The characters transmitted are controlled by the normal transmitter controls. If the transceiver is working properly, the data/control characters transmitted are received by the receiver. This allows system logic to use various data sequences to test the operation of the transceiver. The data is looped back though the primary link path if XCVR_x_RSEL is low and through the redundant path if XCVR_x_RSEL is high. The loop-back signals are electrically isolated from the XLINK0/1_x_P or XLINK0/1_x_N output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. When in loop-back mode, the LBOE signal controls the action of the selected link output signals. When LBOE is low, the XLINK0_x_P / XLINK1_x_P or XLINK0_x_N / XLINK1_x_Noutput signals are undriven and are high-impedance. When LBOE is high, the link output signals enabled by XCVR_x_RSEL continue to operate normally. The receiver's link input signals, RLINK0_x_P / RLINK1_x_P and RLINK0_x_N / RLINK1_x_N, are electrically isolated during loop back mode, such that their state does not affect the loop back path.
5.2.2
BIST Sequence System Test Mode
The MC92610's transmitter has an integrated, 23rd order, Pseudo-Noise (PN) pattern generator. Stimulus from this generator may be used for system testing. The receiver, has a 23rd order signature analyzer that is synchronized to the incoming PN stream and may be used to count character mismatch errors relative to the internal PN reference pattern. This implementation of the 23-bit PN generator and analyzer uses one of the two the polynomials depending on the state of BIST_MODE_SEL: PN Equation 1: f = 1 + x5 + x23 (BIST_MODE_SEL asserted low) PN Equation 2: f = 1 + x18 + x23 (BIST_MODE_SEL asserted high) When inter-operating with Motorola's 1.25 Gbaud SERDES devices (MC92600 or MC92602) use PN equation 1. PN equation 2 is meant for use with external test equipment
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System Accessible Test Modes
that supports this PN equation. Either may be used when inter-operating with another MC92610 device as long as both devices use the same PN equation. In addition to using PN equation 2, setting BIST_MODE_SEL high causes the transmitter to insert 2 Idle characters for every 2048 PN characters transmit. This makes Idles available to be removed to account for frequency offset between devices. The receiver will properly handle the inserted Idles when analyzing the PN character stream. NOTE For the two Idle characters to be inserted, the ADIE signal must be asserted. If the ADIE signal is low, the PN Equation 2 is generated with no inserted Idles. The total mismatch error count is reset to zero when BIST mode is entered. The count is updated continuously while in BIST mode. The value of the count is presented on the receiver interface signals: RECV_x_7 through RECV_x_0, making up the eight-bit error count, ordered bits 7 through 0, respectively. The value of the count is sticky in that the count will not wrap to zero upon overflow, but rather, stays at the maximum count value (11111111). The RECV_x_ERR, RECV_x_K and RECV_x_IDLE, have special meaning during this test mode. They report the status of the receiver and PN analysis logic. Table 5-5 describes the BIST error codes and their meaning. The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode overrides the setting on TBIE signal and forces Byte Interface mode. The BIST sequence requires that a normal byte alignment mode be used. The setting of BSYNC is overridden, forcing the device into the Byte Aligned mode. Also, BIST exercises all transceivers and their transmission paths, ignoring the setting of LME. Finally, the BIST logic operates at the reference clock frequency, all received BIST data is synchronized to the reference clock frequency, overriding the setting of RCCE. BIST is run at the speed indicated by the frequency of the reference clock and by the speed range selected by half-speed mode (HSE). The settings of WSE is not altered and BIST will follow its setting order to properly use this test mode, the system must provide the proper stimulus in a special sequence. The sequence is as follows:
.
Table 5-5. BIST Error Codes
RECV_x_ERR RECV_x_K Low High High Low Low Low RECV_x_IDLE Low Low High Description BIST running, no PN mismatch this character. BIST running, PN mismatch error this character. Receiver byte/word synchronized, PN analyzer is not locked.
MOTOROLA
Chapter 5. Test Features
5-5
Loop-Back BIST Sequence System Test Mode
Table 5-5. BIST Error Codes
High High High High Low High Not Byte Sync: The receiver is in start-up or has lost byte alignment and is searching for alignment. Not Word Sync: The receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment.
Step 1: Enter test mode by setting the test mode inputs as described in Table 5-4. Step 2: Set RESET low and release high; wait PLL lock period (~32 s at 3.125 gigabaud). Step 3: Transmit to the receiver 32 or more Idle (K28.5) characters. Step 4: Transmit to the receiver an 8B/10B encoded PN sequence as described above. The transmitter will automatically go through step 3, transmitting 4,096 Idles, and step 4 upon entering this test mode. When testing is complete, the transceiver will need to be resynchronized before normal operation can resume. NOTE The receiver signature analyzers assume all four channels are being exercised. If BIST testing is being performed between devices, or by means of external loop back on selected channels, the unused channel receivers must be disabled or the analyzers will not go into the PN Sync state. That is, receivers not having an PN stimulus must have XCVR_x_DISABLE asserted. In link multiplexer mode (LME asserted), the secondary receiver interface (channels B and D), must be disabled.
5.3
Loop-Back BIST Sequence System Test Mode
The test mode is the combination of the Loop-Back and BIST Sequence System Test Modes. The device operates as described in Section 5.2.1 and Section 5.2.2. However, the need to go through the startup sequence is eliminated because the transmitter automatically goes through the proper sequence.
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Chapter 6 Electrical Specifications and Characteristics
This chapter explains the electrical specifications and characteristics for the MC92610 device. This chapter consists of the following sections: * * * Section 6.1, "General Characteristics," Section 6.2, "DC Electrical Specifications," and Section 6.3, "AC Electrical Characteristics."
6.1
General Characteristics
This section presents the general technical parameters, the maximum and recommended operating conditions and for the MC92610.
6.1.1
* * * * *
General Parameters
Technology--0.25 lithography, HiP4 CMOS, 5 layer metal Package--324 MAPBGA, 19x19mm Body Size, 1mm Ball Pitch Core Power Supply--1.8V + 0.15V dc HSTL I/O Power Supply--1.5V + 0.1 V dc or 1.8V + 0.15V dc Link I/O Power Supply--1.8V + 0.15V dc
The following provides a summary of the general parameters of the MC92610:
6.1.2
Absolute Maximum Ratings
Table 6-1. Absolute Maximum Ratings
Characteristics 1 Symbol VDD AVDD Min -0.3 -0.3 Max 2.2 2.2 Unit V V
The following Table 6-1, describes the DC electrical characteristics for the MC92610.
Core Supply Voltage PLL Supply Voltage
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-1
General Characteristics
Table 6-1. Absolute Maximum Ratings (continued)
Characteristics 1 HSTL I/O Supply Voltage Link I/O Supply Voltage HSTL Input Voltage CMOS Input Voltage Link Input Voltage Storage Temperature Range Symbol VDDQ XVDD Vin Vin Vin Tstg HBM ESD Tolerance MM
1
Min -0.3 -0.3 -0.3 -0.3 -0.3 -55 2,000 200
Max 2.2 2.2 VDDQ+0.3 VDD+0.3 XVDD+0.3 150 -
Unit V V V V V
oC
V V
Functional and tested operating conditions are given in Table 6-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums are not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
6.1.3
Recommended Operating Conditions
Table 6-2 in this section describes the recommended operating conditions for the MC92610.
Table 6-2. Recommended Operating Conditions
Characteristic 1, 2 Core Supply Voltage PLL Supply Voltage HSTL I/O Supply Voltage (1.5V Operation) HSTL I/O Supply Voltage (1.8V Operation) Link I/O Supply Voltage HSTL Input Voltage CMOS Input Voltage Link Input Voltage Junction Temperature Ambient Temperature 3
1
Symbol VDD AVDD VDDQ VDDQ XVDD Vin Vin Vin Tj Ta
Min 1.65 1.65 1.40 1.65 1.65 0 0 0 -40 -
Max 1.95 1.95 1.60 1.95 1.95 VDDQ VDD XVDD 105 -
Unit V V V V V V V V
oC oC
These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2 Recommended supply power-up order is V , AV , V DD DD DDQ, XVDD, however, any order is acceptable as long as Maximum Ratings are not exceeded. 3 Operating Ambient Temperature is dependent on proper thermal management to meet operating Junction Temperature
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DC Electrical Specifications
6.2
DC Electrical Specifications
Table 6-3. DC Electrical Specifications
Characteristic 1 Symbol IDD AIDD IDDQ XIDD PD VREF VIH DC VIL DC VIH AC VIL AC IIH IIL VOH VOL Cin Rout VIH VIL IIH IIL Cin Rcm Rdiff Rdiff Vcm Min -- -- -- -- -- 0.68 VREF + 0.1 VREF + 0.2 VDDQ-0.4 35 1.0 2 90 75 0.1 Max 1040 10 240 70 -- 0.9 -- VREF - 0.1 VREF - 0.2 80 275 0.4 8 55 0.5 10 10 10 4 115 130 XVDD-0.1 Unit mA mA mA mA mW V V V V V A A V V pF V V A A pF k V
Table 6-3 in this section describes the MC92610's electrical characteristics.
Core Supply Current 2 PLL Supply Current2 HSTL I/O Supply Current2 Link I/O Supply Current2 Total Power Dissipation (typical) 3 HSTL Reference Voltage HSTL Input High Voltage (DC) HSTL Input Low Voltage (DC) HSTL Input High Voltage (AC) HSTL Input Low Voltage (AC) HSTL Input Leakage Current, Vin = VDDQ HSTL Input Leakage Current, Vin = GND HSTL Output High Voltage HSTL Output Low Voltage HSTL Input Capacitance HSTL Output Impedance, Vout = VDDQ/2 CMOS Input High Voltage CMOS Input Low Voltage CMOS Input Leakage Current, Vin = VDDQ CMOS Input Leakage Current, Vin = GND CMOS Input Capacitance Link Common Mode Input Impedance Link Differential Input Impedance (calibration active) Link Differential Input Impedance (calibration disabled) Link Common Mode Input Level 4
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-3
AC Electrical Characteristics
Table 6-3. DC Electrical Specifications (continued)
Characteristic 1 Link Differential Input Amplitude Link Input Capacitance Link Common Mode Output Level Link Differential Output Amplitude, 100 diff load (xmit equalization disabled) Link Differential Output Impedance
1 2
Symbol Vin Cin Vcm Vout Rout
Min 0.2 0.725 900 80
Max 2.2 3 1.075 1350 130
Unit Vp-p pF V mVp-p
VDD = AVDD = XVDD = 1.8 + 0.15 V dc, VDDQ = 1.5 + 0.1 V dc, GND = 0 V dc, -40 < Tj < 105C. Currents maximums at VDD = AVDD = XVDD = VDDQ =1.95 V dc, all links terminated, operating at full-speed. 3 P (typical) mWatts = 208 + 51n + 1.25nf + 3.96f; where n = number of active channels and f = Reference frequency D in MHz. 4 Subject to absolute voltage on link input pin remaining in recommended range per Table 6-2.
6.3
AC Electrical Characteristics
The figures and tables in this section describe the AC electrical characteristics of MC92610. All specifications stated for Tj= -40C to 105C, VDD = AVDD = XVDD = 1.65V to 1.95V, VDDQ = 1.4V to 1.6V.
6.3.1
Parallel Port Interface Timing
The following Figure 6-1 and Table 6-4 describe the transmitter DDR interface timing.
XMIT_x_CLK XMIT_A_CLK XMIT_x_7-XMIT_x_0 XMIT_x_K XMIT_x_IDLE T1 T2 T1 T2
Figure 6-1. Transmitter DDR Interface Timing Table 6-4. Transmitter DDR Timing Specification
Symbol T1 1 T2 1 drift
1
Characteristic Setup time to rising/falling edge of XMIT_x_CLK Hold time to rising/falling edge of XMIT_x_CLK Phase drift between XMIT_x_CLK and REF_CLK_P
Min 0.480 0.480 -180
Max 180
Unit ns ns degrees
156.25MHz operation
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AC Electrical Characteristics
The following Figure 6-2 and Table 6-5 describe the transmitter SDR interface timing.
.
XMIT_x_CLK XMIT_x_7-0 XMIT_x_K XMIT_x_IDLE T1 T2
Figure 6-2. Transmitter Interface SDR Timing Diagram (LME = High, DDRE = Low) Table 6-5. Transmitter SDR Timing Specification (LME = High, DDRE = Low)
Symbol T1 1 T2
1 1
Characteristic Setup time to rising edge of XMIT_x_CLK Hold time to rising edge of XMIT_x_CLK
Min 0.480 0.480
Max -
Unit ns ns
156.25MHz operation
The following Figure 6-3 and Table 6-6 describe the receiver DDR interface timing.
.
RECV_x_CLK RECV_x_7-0 RECV_x_K RECV_x_IDLE RECV_x_ERR RECV_x_9
T1 T2
T1 T2 Tf, Tr
Figure 6-3. Receiver Interface DDR Timing Diagram
Table 6-6. Receiver DDR Timing Specification
Symbol T1 Characteristic Output valid time before rising/falling edge of RECV_x_CLK Min 0.96 1 4.0 2 T2 Output valid time after rising/falling edge of RECV_x_CLK 0.96
1
Max -
Unit ns ns ns ns
0.96 2
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-5
AC Electrical Characteristics
Table 6-6. Receiver DDR Timing Specification (continued)
Symbol Tf 3 Tr 3
1 2
Characteristic Output fall time Output rise time
Min -
Max 1.0 1.0
Unit ns ns
Full speed, 156.25MHz operation (HSE = low). Half-speed, 78.125MHz operation (HSE = high). 3 10pF output load.
The following Figure 6-4 and Table 6-7 describe the receiver SDR interface timing.
.
RECV_x_CLK RECV_x_7-0 RECV_x_K RECV_x_IDLE RECV_x_ERR RECV_x_9
T1
T2
Figure 6-4. Receiver Interface SDR Timing Diagram (LME = High, DDRE = Low) Table 6-7. Receiver SDR Timing Specification (LME = High, DDRE = Low)
Symbol T1 Characteristic Output valid time before rising edge of RECV_x_CLK Min 4.16 1 7.36 2 T2 Output valid time after rising edge of RECV_x_CLK 0.96 1 0.96 2
1 2
Max -
Unit ns ns ns ns
Full speed, 156.25MHz operation (HSE = low). Half-speed, 78.125MHz operation (HSE = high).
6.3.2
Word Synchronization Bus Timing
The following Figure 6-5 and Table 6-8 describe the word synchronization bus timing.
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AC Electrical Characteristics
REF_CLK_P
WSO T1 WSI T3 T4 T2
Figure 6-5. Word Synchronization Bus Timing Diagram Table 6-8. Word Synchronization Bus Timing Specification
Symbol T1 Characteristic Output valid time before rising edge of REF_CLK_P Min 1.25 1, 2 4.45 2, 3 T2 Output valid time after rising edge of REF_CLK_P 1.66 1, 2 1.66 2, 3 T3 T4
1 2
Max -
Unit ns ns ns ns ns ns
Setup time to rising edge of REF_CLK_P Hold time to rising edge of REF_CLK_P
-0.25 1.45
Full speed, 156.25MHz operation (HSE = low). 10 pF output load. 3 Half-speed, 78.125MHz operation (HSE = high).
6.3.3
Reference Clock Timing
The following Figure 6-6 and Table 6-9 describe the reference clock timing.
REF_CLK_N REF_CLK_P Tf, Tr 1/frange Tdiff
Figure 6-6. Reference Clock Timing Diagram
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-7
AC Electrical Characteristics
Table 6-9. Reference Clock Specification
Symbol Tr 1 Tf 1 frange Characteristic REF_CLK_P/N rise time REF_CLK_P/N fall time REF_CLK_P/N frequency range Min 95 2 47.5 3 23.75 4 TD Tdiff ftol Tj 5 Tlock 6
1 2 3 4 5 6
Max 2.0 2.0 156.25 78.125 39.0625 60 1.0 100 80
Unit ns ns MHz MHz MHz Percent ns ppm ps
REF_CLK_P/N duty cycle REF_CLK_P to REF_CLK_N differential skew REF_CLK_P/N frequency tolerance REF_CLK_P/N input jitter PLL lock time
40 -100 -
20,480 + bit-times 25 s
Measured between 10-90 percent points. Full speed operation (HSE = low). Half speed operation, not link multiplexer mode (HSE = high, LME = low) or half speed operation, link multiplexer mode SDR (LME = high, DDRE = low). Half speed operation (HSE = high), link multiplexer mode DDR (LME = high, DDRE = high). Total peak-to-peak jitter. Lock time after compliant REF_CLK_P/N signal applied.
6.3.4
Receiver Recovered Clock Timing
The following Figure 6-7 and Table 6-10 describe the recovered clock timing.
RECV_x_CLK
Tj
Tf, Tr
Trck
Figure 6-7. Recovered Clock Timing Diagram Table 6-10. Recovered Clock Specification
Symbol Trck RECV_x_CLK Characteristic Min 6.20 1, 2 12.44 Tr 4 Tf
4 3
Max 1.0 1.0
Unit ns ns ns ns
RECV_x_RCLK rise time RECV_x_CLK fall time
-
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AC Electrical Characteristics
Table 6-10. Recovered Clock Specification (continued)
Symbol Tj RECV_x_CLK jitter Characteristic Min 1 2
Max 400 1, 5 720 3, 5
Unit ps ps
Measured between 50-50 percent points, 156.25MHz REF_CLK, full speed DDR (HSE = low). Includes jitter component. 3 Measured between 50-50 percent points, 78.125MHz REF_CLK, half speed DDR (HSE = high). 4 Measured between 10-90 percent points. 5 Total peak-to-peak jitter.
6.3.5
Serial Data Link Timing
The following Figure 6-8 and Table 6-11 describe the link differential output timing.
XLINK0/1_x_P XLINK0/1_x_N Tj Tds
Figure 6-8. Link Differential Output Timing Diagram Table 6-11. Link Differential Output Specification
Symbol Tj 1 Tdj 1 Tds 1 Xla 2t
1 2
Characteristic Total jitter Deterministic jitter Differential skew Transmit latency
Min 150
Max 0.35 0.17 15 190
Unit UI UI ps bit-times
Measured between 50-50 percent points. Rising edge REF_CLK_P to bit 0 transmit.
The following Figure 6-9 and Table 6-12 describe the link differential output timing.
RLINK0/1_x_P RLINK0/1_x_N Tjtol Tdstol
Figure 6-9. Link Differential Input Timing Diagram
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-9
AC Electrical Characteristics
Table 6-12. Link Differential Input Timing Specification
Symbol Tjtol 1, 2 Total jitter tolerance Tdjtol 1 Tdstol 1 Rlat Deterministic jitter tolerance Differential skew tolerance Receive latency Characteristic Min 0.70 0.36 75 270 Tacq
1 2 3 4 5 6
Max 340 3 400 4 440 5 300 6
Unit UI UI ps bit-times bit-times bit-times bit-times
Receiver phase acquisition time
-
Measured between 50-50 percent points. Includes 0.1 UI of band-limited sinusoidal noise, 1.875Mhz < fnoise < 20MHz. Bit 0 at receiver input to parallel data out, no word synchronization. Bit 0 at receiver input to parallel data out, single-chip word synchronization. Bit 0 at receiver input to parallel data out, multi-chip word synchronization. Measured with worst-case eye opening, Idle pattern, and reference PLL locked.
6.3.6
JTAG Test Port Timing
The following Figure 6-10 and Table 6-13 describe the JTAG test port timing.
TCK
1/fTCK
TDO T1 TDI TMS T2 T3
Figure 6-10. JTAG I/O Timing Diagram
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AC Electrical Characteristics
Table 6-13. JTAG I/O Timing Specification
Symbol T1 1 T2 T3 fTCK TD
1
Characteristic Output propagation time after falling edge of TCK Setup time to rising edge of TCK Hold time to rising edge of TCK TCK frequency TCK duty cycle
Min 1.0 1.0 0.5 35
Max 8.0 20 65
Unit ns ns ns MHz Percent
Note 1
10 pF output load
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-11
AC Electrical Characteristics
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MOTOROLA
Chapter 7 Package Description
The following section provides the package parameters and mechanical dimensions of the MC92610 device. The MC92610 is offered in a 324 MAPBGA package. The 324 MAPBGA utilizes an aggressive 1 mm ball pitch and 19 mm body size for applications where board space is limited.
7.1
* * * * * *
324 MAPBGA Package Parameter Summary
Package Type--MAP Ball Grid Array Package Outline--19 mm x 19 mm Package Height--1.76 mm (typ.) Number of Balls--324 Ball Pitch--1 mm Ball Diameter--0.63 mm (typ.)
7.2
Nomenclature and Dimensions of the 324 MAPBGA Package
Figure 7-1 provides the bottom surface nomenclature and package outline drawing of the 324 MAPBGA package. Figure 7-2 provides the package dimensions. Figure 7-3 provides a graphic of the package pin to signal mappings.
MOTOROLA
Chapter 7. Package Description
7-1
Nomenclature and Dimensions of the 324 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT MOTOROLA, INC. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING D
DOCUMENT NO: PAGE: REV: A 1344 DATE:
98ASA99230D 30 AUG 01
X Y
M DETAIL K
(SHEET 2 OF 2)
A1 INDEX AREA
E
4X 0.10
TOP VIEW 17X e S
V U T R P N M L K J H G F E D C B A
M
17X e
S
324X
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
b
3 ZXY Z
A1 INDEX AREA TITLE
0.25 M 0.10 M
BOTTOM VIEW
VIEW M-M
324 I/O PBGA, 19 X 19 PKG, 1.00 PITCH (THICK MAP)
CASE NUMBER: STANDARD: PACKAGE CODE:
1344-02 5231 SHEET: 1 OF 2
JEDEC MS-034 AAG-1
Figure 7-1. 324 MAPBGA Nomenclature
7-2 MC92610 SERDES User's Manual MOTOROLA
Nomenclature and Dimensions of the 324 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT MOTOROLA, INC. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING
DOCUMENT NO: PAGE: REV: A 1344 DATE:
98ASA99230D 30 AUG 01
5 0.25 A2 Z
A
324X
A1 Z 4 0.20 Z
DETAIL K
VIEW ROTATED 90 CLOCKWISE
DIM A A1 A2 b D E e S
MIN 1.66 0.45 1.26 REF
MAX 1.86 0.55 1 2 3
NOTES DIMENSIONS ARE IN MILLIMETERS. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
0.50 19.00 BSC
0.70 4 19.00 BSC 1.00 BSC 0.50 BSC 5
TITLE
324 I/O PBGA, 19 X 19 PKG, 1.00 PITCH (THICK MAP)
CASE NUMBER: STANDARD: PACKAGE CODE:
1344-02 5231 SHEET: 2 OF 2
JEDEC MS-034 AAG-1
Figure 7-2. MAPBGA Dimensions
MOTOROLA Chapter 7. Package Description 7-3
Nomenclature and Dimensions of the 324 MAPBGA Package
.
1 V U T R P N M L K J H G F E D C B A
PADVDD COREGND/ PADGND RECV_ A_6 RECV_ A_2 RECV_ B_0 RECV_ B_3 RECV_ B_6
2
RECV_ A_ERR RECV_ A_IDLE RECV_ A_7
3
XMIT_ B_K XMIT_ B_IDLE RECV_ A_K
4
XMIT_ B_CLK XMIT_ B_4 XMIT_ B_6 XMIT_ B_7 RECV_ A_9
5
XMIT_ B_1 XMIT_ B_2 XMIT_ B_3 XMIT_ B_5
6
7
8
9
XMIT_ A_IDLE TST_1
10
TBIE SCAN_ EN RESET
11
TMS
12
TCK XMIT_ REF_A RECV_ REF_A
13
14
15
16
17
18 V U T R P N M L K J H G F E D C B A
DROP_ COREVDD COREGND/ PADGND SYNC XMIT_ A_1 XMIT_ A_0 XMIT_ B_0 XMIT_ A_CLK XMIT_ A_4 XMIT_ A_2 XMIT_ A_K XMIT_ A_7 XMIT_ A_5
COREVDD COREGND/ COREVDD RLINK_ COREVDD RLINK_ A1_N A0_N PADGND XCVR_ B_RSEL XMIT_ COREGND/ RLINK_ COREGND/ RLINK_ EQ_EN PADGND A1_P PADGND A0_P
TDI
TST_0 BIST_ MODE_ SEL XMIT_ A_6
TRST
XCVR_ COREGND/ XLINK_ XPADVDD XLINK_ XPADGND C_RSEL PADGND A1_N A0_N
PADVDD RECV_ A_3
BSYNC
TDO
XLINK_ XLINK_ XPADV RECV_ COREGND/ COREV DD DD A1_P XPADGND A0_P EQ_EN PADGND XCVR_ COREV COREV XPADVDD XLINK_ XPADGND XLINK_ DD DD D_RSEL B1_N B0_N
RECV_ A_0
RECV_ A_1
XMIT_ RECV_ COREV COREV DD DD A_3 A_CLK
COREVDD XCVR_ A_RSEL
PADVDD RECV_ B_2 RECV_ B_5 RECV_ B_4 RECV_ B_7 RECV_ B_CLK
RECV_ COREV COREV COREV COREV COREV COREV XLINK_ XLINK_ DD COREVDD COREVDD COREGND/ COREVDD XPADGND B1_P XPADVDD B0_P DD DD DD DD DD A_5 PADGND RECV_ COREV RLINK_ COREV RLINK_ COREV COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ DD PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND COREVDD B1_N DD B0_N DD A_4 RECV_ COREV RLINK_ COREGND/ RLINK_ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREV DDD PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND DD B1_P B0_P PADGND B_1 PADGND RECV_ B_IDLE HSTL_ VREF TX_PLL_ TX_ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREV XPADGND COREGND/ DD TPA PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND PLLVDD
PADVDD RECV_ B_K COREGND/ RECV_ B_9 PADGND RECV_ B_ERR RECV_ C_IDLE RECV_ C_7 RECV_ C_4 RECV_ C_0 RECV_ D_2 RECV_ C_ERR RECV_ C_CLK
PADVDD RECV_ COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREVDD COREGND/ XPADVDD COREVDD TX_ PLLGND C_K PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND RECV_ C_9 RECV_ C_5 COREDD COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREVDD RLINK_ COREVDD RLINK_ Z_CALIB C0_P C1_P PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADVDD COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREGND/ COREVDD RLINK_ COREGND/ RLINK_ COREVDD C1_N PADGND C0_ N PADGND PADGND PADGND PADGND PADGND PADGND PADGND PADGND
RECV_ RECV_ PADV DD C_1 C_6 RECV_ C_3 RECV_ D_0 RECV_ D_3
RECV_ COREV COREV COREV COREV COREV COREV COREV COREVDD COREVDD COREGND/ COREVDD XPADVDD XLINK_ XPADVDD XLINK_ DD DD DD DD DD DD DD C_2 C1_P C0_P PADGND RECV_ COREV COREV COREV COREV XMIT_ DD DD DD DD C_1 D_1 RECV_ D_4 RECV_ D_9 PADVDD RECV_ D_ERR RECV_ D_CLK WSO RECV_ D_K XMIT_ C_7 XMIT_ C_5 XMIT_ C_K XMIT_ C_IDLE XMIT_ C_2 XMIT_ C_4 XMIT_ C_3 XMIT_ D_0 XMIT_ D_2 XMIT_ C_CLK XMIT_ D_1 XMIT_ D_3 XMIT_ D_6 XMIT_ D_5 XMIT_ C_0 XMIT_ D_4 XMIT_ D_7 XMIT_ D_K ADIE COREVDD COREVDD COREVDD COREVDD XPADGND XLINK_ XPADGND XLINK_ C1_N C0_N RCCE LME XMIT_ EN_ALL LBE XCVR_A_ COREV XLINK_ XPADGND XLINK_ COREV DD D1_P DD DISABLE D0_P HSE XCVR_B_ XLINK_ XPADV XLINK_ DD D0_N XPADVDD DISABLE D1_N XCVR_C_ COREV RLINK_ RLINK_ DD D1_P XPADGND D0_P DISABLE XCVR_D_ COREGND/ RLINK_ COREGND/ RLINK_ DISABLE PADGND D1_N PADGND D0_N
WSE XMIT_ D_IDLE XMIT_ D_CLK
PADVDD RECV_ D_5 COREGND/ RECV_ D_6 PADGND RECV_ D_7 RECV_ D_IDLE
REPE
WSI XMIT_ C_6
LBOE
DDRE REF_ CLK_P
COREVDD COREGND/ PADGND
COREVDD COREGND/ REF_ PADGND CLK_N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VIEW M-M (BOTTOM VIEW)
Figure 7-3. 324 MAPBGA Package
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MC92610 SERDES User's Manual
MOTOROLA
Package Thermal Characteristics
7.3
Package Thermal Characteristics
Thermal values for the 324 pin MAPBGA are listed below in Table 7-1. The values listed below assume the customer will be mounting these packages on a thermally enhanced mother board. This is defined as a minimum 4-layer board with one ground plane. The values listed below were simulated in accordance with established JEDEC (Joint Electron Device Engineering Council) standards.
.
Table 7-1. Package Thermal Resistance Values
Symbol Description Thermal resistance from junction to ambient, still air Value 23
o
Units
ja-0 ja-2 ja-4
1
CW
Thermal resistance from junction to ambient, 200 LFM 1
20
o
CW
Thermal resistance from junction to ambient, 400 LFM 1
19
o
CW
Linear feet per minute
7.4
MC92610 Chip Pinout Listing
The MC92610 is offered in a 324 MAPBGA package. Table 7-2 lists the MC92610 signal to ball location mappings for the package. Also shown are signaling direction (input or output), and the type of logic interfaces.
Table 7-2. 324 MAPBGA Signal to Ball Mapping
Signal Name XMIT_A_0 XMIT_A_1 XMIT_A_2 XMIT_A_3 XMIT_A_4 XMIT_A_5 XMIT_A_6 XMIT_A_7 XMIT_A_K XMIT_A_IDLE Description Transmitter A, Data bit 0 Transmitter A, Data bit 1 Transmitter A, Data bit 2 Transmitter A, Data bit 3 Transmitter A, Data bit 4 Transmitter A, Data bit 5 Transmitter A, Data bit 6 Transmitter A, Data bit 7 Transmitter A, Special Character (Data bit 8 for TBI mode) Transmitter A, Idle Enable Bar, (Data bit 9 for TBI mode) Ball Number (324 MAPBGA) T6 U6 R7 P8 T7 R8 P9 T8 U8 V9 Direction Input Input Input Input Input Input Input Input Input Input I/O Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL
MOTOROLA
Chapter 7. Package Description
7-5
MC92610 Chip Pinout Listing
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name XMIT_A_CLK RECV_A_0 RECV_A_1 RECV_A_2 RECV_A_3 RECV_A_4 RECV_A_5 RECV_A_6 RECV_A_7 RECV_A_K RECV_A_9 RECV_A_IDLE RECV_A_ERR RECV_A_CLK XCVR_A_RSEL XCVR_A_DISABLE RLINK_A0_P RLINK_A0_N RLINK_A1_P RLINK_A1_N XLINK_A0_P XLINK_A0_N XLINK_A1_P XLINK_A1_N XMIT_B_0 XMIT_B_1 XMIT_B_2 XMIT_B_3 XMIT_B_4 XMIT_B_5 XMIT_B_6 XMIT_B_7 Description Transmitter A, Transmit Interface Clock Receiver A, Data bit 0 Receiver A, Data bit 1 Receiver A, Data bit 2 Receiver A, Data bit 3 Receiver A, Data bit 4 Receiver A, Data bit 5 Receiver A, Data bit 6 Receiver A, Data bit 7 Receiver A, Special Character (Data bit 8 for TBI mode) Receiver A, Data bit 9 for TBI mode Receiver A, Idle Detect Receiver A, Error Detect Receiver A, Receive Data Clock Transceiver A, Redundant Link Select Transceiver A, Disable Receiver A, Primary Positive Link Input Receiver A, Primary Negative Link Input Receiver A, Redundant Positive Link Input Receiver A, Redundant Negative Link Input Transmitter A, Primary Positive Link Out Transmitter A, Primary Negative Link Out Transmitter A, Redundant Positive Link Out Transmitter A, Redundant Negative Link Out Transmitter B, Data bit 0 Transmitter B, Data bit 1 Transmitter B, Data bit 2 Transmitter B, Data bit 3 Transmitter B, Data bit 4 Transmitter B, Data bit 5 Transmitter B, Data bit 6 Transmitter B, Data bit 7 Ball Number (324 MAPBGA) U7 P2 P3 R1 R3 M4 N4 T1 T2 T3 P4 U2 V2 P5 P11 D13 U18 V18 U16 V16 R17 T17 R15 T15 R6 V5 U5 T5 U4 R5 T4 R4 Direction Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Output Output Output Output Input Input Input Input Input Input Input Input I/O Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL CMOS CMOS Link Link Link Link Link Link Link Link HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL
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MC92610 Chip Pinout Listing
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name XMIT_B_K XMIT_B_IDLE XMIT_B_CLK RECV_B_0 RECV_B_1 RECV_B_2 RECV_B_3 RECV_B_4 RECV_B_5 RECV_B_6 RECV_B_7 RECV_B_K RECV_B_9 RECV_B_IDLE RECV_B_ERR RECV_B_CLK XCVR_B_RSEL XCVR_B_DISABLE RLINK_B0_P RLINK_B0_N RLINK_B1_P RLINK_B1_N XLINK_B0_P XLINK_B0_N XLINK_B1_P XLINK_B1_N XMIT_C_0 XMIT_C_1 XMIT_C_2 XMIT_C_3 XMIT_C_4 Description Transmitter B, Special Character (Data bit 8 for TBI mode) Transmitter B, Idle Enable Bar, (Data bit 9 for TBI mode) Transmitter B, Transmit Interface Clock Receiver B, Data bit 0 Receiver B, Data bit 1 Receiver B, Data bit 2 Receiver B, Data bit 3 Receiver B, Data bit 4 Receiver B, Data bit 5 Receiver B, Data bit 6 Receiver B, Data bit 7 Receiver B, Special Character (Data bit 8 for TBI mode) Receiver B, Data bit 9 for TBI mode Receiver B, Idle Detect Receiver B, Error Detect Receiver B, Receive Data Clock Transceiver B, Redundant Link Select Transceiver B, Disable Receiver B, Primary Positive Link Input Receiver B, Primary Negative Link Input Receiver B, Redundant Positive Link Input Receiver B, Redundant Negative Link Input Transmitter B, Primary Positive Link Out Transmitter B, Primary Negative Link Out Transmitter B, Redundant Positive Link Out Transmitter B, Redundant Negative Link Out Transmitter C, Data bit 0 Transmitter C, Data bit 1 Transmitter C, Data bit 2 Transmitter C, Data bit 3 Transmitter C, Data bit 4 Ball Number (324 MAPBGA) V3 U3 V4 P1 L4 N3 N1 M3 M2 M1 L3 L2 K2 K4 J1 K3 U13 C14 L17 M17 L15 M15 N18 P18 N16 P16 D9 E8 B6 C7 D7 Direction Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Output Output Output Output Input Input Input Input Input I/O Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL CMOS CMOS Link Link Link Link Link Link Link Link HSTL HSTL HSTL HSTL HSTL
MOTOROLA
Chapter 7. Package Description
7-7
MC92610 Chip Pinout Listing
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name XMIT_C_5 XMIT_C_6 XMIT_C_7 XMIT_C_K XMIT_C_IDLE XMIT_C_CLK RECV_C_0 RECV_C_1 RECV_C_2 RECV_C_3 RECV_C_4 RECV_C_5 RECV_C_6 RECV_C_7 RECV_C_K RECV_C_9 RECV_C_IDLE RECV_C_ERR RECV_C_CLK XCVR_C_RSEL XCVR_C_DISABLE RLINK_C0_P RLINK_C0_N RLINK_C1_P RLINK_C1_N XLINK_C0_P XLINK_C0_N XLINK_C1_P XLINK_C1_N XMIT_D_0 XMIT_D_1 Description Transmitter C, Data bit 5 Transmitter C, Data bit 6 Transmitter C, Data bit 7 Transmitter C, Special Character (Data bit 8 for TBI mode) Transmitter C, Idle Enable Bar, (Data bit 9 for TBI mode) Transmitter C, Transmit Interface Clock Receiver C, Data bit 0 Receiver C, Data bit 1 Receiver C, Data bit 2 Receiver C, Data bit 3 Receiver C, Data bit 4 Receiver C, Data bit 5 Receiver C, Data bit 6 Receiver C, Data bit 7 Receiver C, Special Character (Data bit 8 for TBI mode) Receiver C, Data bit 9 for TBI mode Receiver C, Idle Detect Receiver C, Error Detect Receiver C, Receive Data Clock Transceiver C, Redundant Link Select Transceiver C, Disable Receiver C, Primary Positive Link Input Receiver C, Primary Negative Link Input Receiver C, Redundant Positive Link Input Receiver C, Redundant Negative Link Input Transmitter C, Primary Positive Link Out Transmitter C, Primary Negative Link Out Transmitter C, Redundant Positive Link Out Transmitter C, Redundant Negative Link Out Transmitter D, Data bit 0 Transmitter D, Data bit 1 Ball Number (324 MAPBGA) B5 A4 C5 D6 C6 D8 E1 G4 F3 F2 F1 H4 G2 G1 J4 H3 H1 J2 H2 T13 B14 H17 G17 H15 G15 F18 E18 F16 E16 B7 C8 Direction Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Output Output Output Output Input Input I/O Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL CMOS CMOS Link Link Link Link Link Link Link Link HSTL HSTL
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MC92610 Chip Pinout Listing
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name XMIT_D_2 XMIT_D_3 XMIT_D_4 XMIT_D_5 XMIT_D_6 XMIT_D_7 XMIT_D_K XMIT_D_IDLE XMIT_D_CLK RECV_D_0 RECV_D_1 RECV_D_2 RECV_D_3 RECV_D_4 RECV_D_5 RECV_D_6 RECV_D_7 RECV_D_K RECV_D_9 RECV_D_IDLE RECV_D_ERR RECV_D_CLK XCVR_D_RSEL XCVR_D_DISABLE RLINK_D0_P RLINK_D0_N RLINK_D1_P RLINK_D1_N XLINK_D0_P XLINK_D0_N XLINK_D1_P Description Transmitter D, Data bit 2 Transmitter D, Data bit 3 Transmitter D, Data bit 4 Transmitter D, Data bit 5 Transmitter D, Data bit 6 Transmitter D, Data bit 7 Transmitter D, Special Character (Data bit 8 for TBI mode) Transmitter D, Idle Enable Bar, (Data bit 9 for TBI mode) Transmitter D, Transmit Interface Clock Receiver D, Data bit 0 Receiver D, Data bit 1 Receiver D, Data bit 2 Receiver D, Data bit 3 Receiver D, Data bit 4 Receiver D, Data bit 5 Receiver D, Data bit 6 Receiver D, Data bit 7 Receiver D, Special Character (Data bit 8 for TBI mode) Receiver D, Data bit 9 for TBI mode Receiver D, Idle Detect Receiver D, Error Detect Receiver D, Receive Data Clock Transceiver D, Redundant Link Select Transceiver D, Disable Receiver D, Primary Positive Link Input Receiver D, Primary Negative Link Input Receiver D, Redundant Positive Link Input Receiver D, Redundant Negative Link Input Transmitter D, Primary Positive Link Out Transmitter D, Primary Negative Link Out Transmitter D, Redundant Positive Link Out Ball Number (324 MAPBGA) A7 B8 C9 E9 A8 B9 A9 C10 B10 E2 E3 D1 D2 D3 C2 B2 A1 D5 C3 A2 A3 D4 P12 A14 B18 A18 B16 A16 D17 C17 D15 Direction Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Output Output Output I/O Type HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL HSTL CMOS CMOS Link Link Link Link Link Link Link
MOTOROLA
Chapter 7. Package Description
7-9
MC92610 Chip Pinout Listing
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name XLINK_D1_N DROP_SYNC XMIT_REF_A RECV_REF_A XMIT_EQ_EN RECV_EQ_EN XMIT_EN_ALL TBIE HSE DDRE BSYNC ADIE REPE LME RCCE REF_CLK_P REF_CLK_N RESET WSE WSO WSI TX_PLL_TPA TST_0 TST_1 SCAN_EN LBE LBOE BIST_MODE_SEL TDO TMS TDI TRST TCK Description Transmitter D, Redundant Negative Link Out Drop Synchronization Transmitter Reference Clock A Select Receiver Reference Clock A Select Transmitter Equalization Enable Receiver Equalization Enable Transmitter Enable, All Outputs Ten-Bit Interface Enable Half Speed Enable Double Data Rate Enable Byte Synchronization Mode Add/Drop Idle Enable Repeater Mode Enable Link Multiplexer Mode Enable Recovered Clock Enable Reference Clock Positive Reference Clock Negative System Reset Bar Word Synchronization Enable Word Synchronization Bus Output Word Synchronization Bus Input PLL Analog Test Point Test Mode Select 0 Test Mode Select 1 Test Mode, Scan Shift Enable Loop Back Enable Loop Back Output Enable BIST Mode Equation Select JTAG Test Data Out JTAG Test Mode Select JTAG Test Data In JTAG Test Reset Bar JTAG Test Clock Ball Number (324 MAPBGA) C15 V8 U12 T12 U14 R12 C12 V10 C13 B13 R10 E10 C11 D12 D11 A13 A12 T10 D10 C4 B4 K15 T9 U9 U10 B12 B11 R9 R11 V11 U11 T11 V12 Direction Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Input Input Input Input Input Output Input Input Input Input I/O Type Link HSTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS HSTL HSTL CMOS CMOS HSTL HSTL Analog CMOS CMOS CMOS CMOS CMOS CMOS HSTL CMOS CMOS CMOS CMOS
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MC92610 Chip Pinout Listing
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name Z_CALIB HSTL_VREF COREVDD Description Impedance Calibration Reference HSTL Voltage Reference Core logic supply Ball Number (324 MAPBGA) H18 K5 A5, A10, B15, D14, D18, E4, E5, E6, E7, E11, E12, E13, E14, F4, F5, F6, F7, F8, F9, F10, F11, F12, F14, G14, G18, H5, H14, H16, J5, J14, J17, K14, L5, L14, M5, M14, M16, M18, N5, N6, N7, N8, N9, N10, N11, N12, N14, P6, P7, P10, P13, P14, R14, V6, V13, V15, V17 A6, A11, A15, A17, B1, F13, G6, G7, G8, G9, G10, G11, G12, G13, G16, H6, H7, H8, H9, H10, H11, H12, H13, J6, J7, J8, J9, J10, J11, J12, J13, J15, K1, K6, K7, K8, K9, K10, K11, K12, K13, K17, L6, L7, L8, L9, L10, L11, L12, L13, L16, L18, M6, M7, M8, M9, M10, M11, M12, M13, N13, R13, T14, U1, U15, U17, V7, V14 K18 J18 B3, C1, G3, G5, J3, L1, N2, R2, V1 C16, C18, F15, F17, J16, N17, P15, R18, T16 B17, D16, E15, E17, K16, P17, N15, R16, T18 Direction ZREF VREF VDD I/O Type Analog Analog Supply
COREGND/PADGND
Core logic ground / HSTL I/O ground
GND
Ground
TX_PLLVDD TX_PLLGND PADVDD
PLL analog supply PLL analog ground HSTL I/O supply Link I/O supply
AVDD GND VDDQ XVDD
Supply Ground Supply Supply
XPADVDD Link I/O ground XPADGND
GND
Ground
MOTOROLA
Chapter 7. Package Description
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MC92610 Chip Pinout Listing
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MOTOROLA
Appendix A Ordering Information
Figure A-1 provides the Motorola part numbering nomenclature for the MC92610. For product availability, contact your local Motorola Semiconductor sales representative.
MC92610VF
Product Code: MC = Production Product Part Identifier Package: VF = 324 pin MAPBGA
Figure A-1. Motorola Part Number Key
MOTOROLA
Appendix A. Ordering Information
A-1
A-2
MC92610 SERDES User's Manual
MOTOROLA
Appendix B 8B/10B Coding Scheme
The MC92610 provides fibre channel-specific 8B/10B encoding and decoding based on the FC-1 fibre channel standard. Given 8 bits entering a channel, the 8B/10B encoding converts them to 10 bits thereby increasing the transition density of the serially transmitted signal.
B.1
Overview
The FC-1 standard applies an algorithm that ensures that no more than five 1's or 0's are transmitted consecutively, giving a transition density equal to 2.5 for each 10 bit data block. Such a density ensures proper DC balance across the link and is sufficient for good clock recovery. In the 8B/10B notation scheme, bytes are referred to as transmission characters, and each bit is represented by letters. Unencoded bits, the 8 bits that have not passed through a 8B/10B encoder, are represented by letters "A" through "H," which are bits 0 through7.
One unencoded transmission character (Byte) H Bit 7 G Bit 6 F Bit 5 E Bit 4 D Bit 3 C Bit 2 B Bit 1 A Bit 0 lsb
Figure B-1. Unencoded Transmission Character Bit Ordering
Encoded bits, those that have passed through an encoder, are represented with the letters "a" through "j," representing bits 0-9 respectively. Character (bit) ordering in the fibre channel nomenclature is little-endian, with "a" being the least significant bit in a byte.
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-1
Overview
One coded transmission character (Byte) j Bit 9 h Bit 8 g Bit 7 f Bit 6 i Bit 5 e Bit 4 d Bit 3 c Bit 2 b Bit 1 a Bit 0 lsb
Figure B-2. Encoded Transmission Character Bit Ordering
B.1.1
Naming Transmission Characters
Transmission characters are given names based on the type of data in the byte and the bit values of the character. Two types of transmission characters are specified: data and special. Data characters are labeled "D" characters and special characters are labeled "K" characters. Each transmission character has a bit value and a corresponding decimal value. These elements are combined to provide each character with a name, see Table B-1.
Table B-1. Components of a Character Name
HGF 001 1 D or K EDCBA 11100 28 8B/10B notation Data bit value Decimal value of the bit value Kind of transmission character
K28.1 = Data name assigned to this special character
B.1.2
Encoding
Following is a simplified sequence of steps in 8B/10B coding: 1. An 8-bit block of unencoded data (a transmission character) is picked up by a transmitter. 2. The transmission character is broken into sub-blocks of three bits and five bits. The letters H G and F comprise the 3-bit block, and the letters E D C B and A comprise the 5-bit block. 3. The 3-bit and 5-bit sub-blocks pass through a 3B/4B encoder and a 5B/6B encoder, respectively. A bit is added to each sub-block, such that the transmission character is encoded and expanded to a total of 10-bits. 4. At the time the character is expanded into 10 bits, it is also encoded into the proper running disparity, either positive (RD+) or negative (RD-) depending on certain calculations (see Section B.1.3, "Calculating Running Disparity"). At start-up, the transmitter assumes negative running disparity.
B-2
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Data Tables
5. The positive or negative disparity transmission character (see Figure B-3) is passed to the transmit driver, available for differentialization (See Section 2.3.1.7, "Transmit Driver Operation").
J H G F I E D C B A
Direction of Transmission
Figure B-3. Character Transmission
B.1.3
Calculating Running Disparity
Running disparity improves error detection and recovery. The rules for calculating the running disparity for sub-blocks are as follows (reference Fibre Channel, Gigabit Communications and I/O for Computer Networks): * Running disparity at the end of any sub-block is positive if (1) the encoded sub-block contains more 1s than 0s, (2) if the 6-bit sub-block is 6'b00 0111, or (3) if the 4-bit sub-block is 4'b0011. Running disparity at the end of any sub-block is negative if (1) the encoded sub-block contains more 0 than 1 bits, (2) if the 6-bit sub-block is 6'b11 1000, or (3) if the 4-bit sub-block is 4'b1100. Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.
*
*
B.2
Data Tables
Table B-2 displays the full valid data character 8B/10B codes. The values in the "Data Value HGFEDCBA" column are the possible bit values of the unencoded transmission characters. The current RD values are the possible positive and negative running disparity values.
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-3
Data Tables
Table B-2. Valid Data Characters
Data Name D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0 D12.0 D13.0 D14.0 D15.0 D16.0 D17.0 D18.0 D19.0 D20.0 D21.0 D22.0 D23.0 D24.0 D25.0 D26.0 D27.0 D28.0 D29.0 D30.0 D31.0 D0.2 Data Value
HGF EDCBA
Current RDabcdei fghj 100111 0100 011101 0100 101101 0100 110001 1011 110101 0100 101001 1011 011001 1011 111000 1011 111001 0100 100101 1011 010101 1011 110100 1011 001101 1011 101100 1011 011100 1011 010111 0100 011011 0100 100011 1011 010011 1011 110010 1011 001011 1011 101010 1011 011010 1011 111010 0100 110011 0100 100110 1011 010110 1011 110110 0100 001110 1011 101110 0100 011110 0100 101011 0100 100111 0101
Current RD+ abcdei fghj 011000 1011 100010 1011 010010 1011 110001 0100 001010 1011 101001 0100 011001 0100 000111 0100 000110 1011 100101 0100 010101 0100 110100 0100 001101 0100 101100 0100 011100 0100 101000 1011 100100 1011 100011 0100 010011 0100 110010 0100 001011 0100 101010 0100 011010 0100 000101 1011 001100 1011 100110 0100 010110 0100 001001 1011 001110 0100 010001 1011 100001 1011 010100 1011 011000 0101
Data Name D0.1 D1.1 D2.1 D3.1 D4.1 D5.1 D6.1 D7.1 D8.1 D9.1 D10.1 D11.1 D12.1 D13.1 D14.1 D15.1 D16.1 D17.1 D18.1 D19.1 D20.1 D21.1 D22.1 D23.1 D24.1 D25.1 D26.1 D27.1 D28.1 D29.1 D30.1 D31.1 D0.3
Data Value
HGF EDCBA
Current RDabcdei fghj 100111 1001 011101 1001 101101 1001 110001 1001 110101 1001 101001 1001 011001 1001 111000 1001 111001 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 010111 1001 011011 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 111010 1001 110011 1001 100110 1001 010110 1001 110110 1001 001110 1001 101110 1001 011110 1001 101011 1001 100111 0011
Current RD+ abcdei fghj 011000 1001 100010 1001 010010 1001 110001 1001 001010 1001 101001 1001 011001 1001 000111 1001 000110 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 101000 1001 100100 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 000101 1001 001100 1001 100110 1001 010110 1001 001001 1001 001110 1001 010001 1001 100001 1001 010100 1001 011000 1100
000 00000 000 00001 000 00010 000 00011 000 00100 000 00101 000 00110 000 00111 000 01000 000 01001 000 01010 000 01011 000 01100 000 01101 000 01110 000 01111 000 10000 000 10001 000 10010 000 10011 000 10100 000 10101 000 10110 000 10111 000 11000 000 11001 000 11010 000 11011 000 11100 000 11101 000 11110 000 11111 010 00000
001 00000 001 00001 001 00010 001 00011 001 00100 001 00101 001 00110 001 00111 001 01000 001 01001 001 01010 001 01011 001 01100 001 01101 001 01110 001 01111 001 10000 001 10001 001 10010 001 10011 001 10100 001 10101 001 10110 001 10111 001 11000 001 11001 001 11010 001 11011 001 11100 001 11101 001 11110 001 11111 011 00000
B-4
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MOTOROLA
Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D1.2 D2.2 D3.2 D4.2 D5.2 D6.2 D7.2 D8.2 D9.2 D10.2 D11.2 D12.2 D13.2 D14.2 D15.2 D16.2 D17.2 D18.2 D19.2 D20.2 D21.2 D22.2 D23.2 D24.2 D25.2 D26.2 D27.2 D28.2 D29.2 D30.2 D31.2 D0.4 D1.4 Data Value
HGF EDCBA
Current RDabcdei fghj 011101 0101 101101 0101 110001 0101 110101 0101 101001 0101 011001 0101 111000 0101 111001 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 010111 0101 011011 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 111010 0101 110011 0101 100110 0101 010110 0101 110110 0101 001110 0101 101110 0101 011110 0101 101011 0101 100111 0010 011101 0010
Current RD+ abcdei fghj 100010 0101 010010 0101 110001 0101 001010 0101 101001 0101 011001 0101 000111 0101 000110 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 101000 0101 100100 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 000101 0101 001100 0101 100110 0101 010110 0101 001001 0101 001110 0101 010001 0101 100001 0101 010100 0101 011000 1101 100010 1101
Data Name D1.3 D2.3 D3.3 D4.3 D5.3 D6.3 D7.3 D8.3 D9.3 D10.3 D11.3 D12.3 D13.3 D14.3 D15.3 D16.3 D17.3 D18.3 D19.3 D20.3 D21.3 D22.3 D23.3 D24.3 D25.3 D26.3 D27.3 D28.3 D29.3 D30.3 D31.3 D0.5 D1.5
Data Value
HGF EDCBA
Current RDabcdei fghj 011101 0011 101101 0011 110001 1100 110101 0011 101001 1100 011001 1100 111000 1100 111001 0011 100101 1100 010101 1100 110100 1100 001101 1100 101100 1100 011100 1100 010111 0011 011011 0011 100011 1100 010011 1100 110010 1100 001011 1100 101010 1100 011010 1100 111010 0011 110011 0011 100110 1100 010110 1100 110110 0011 001110 1100 101110 0011 011110 0011 101011 0011 100111 1010 011101 1010
Current RD+ abcdei fghj 100010 1100 010010 1100 110001 0011 001010 1100 101001 0011 011001 0011 000111 0011 000110 1100 100101 0011 010101 0011 110100 0011 001101 0011 101100 0011 011100 0011 101000 1100 100100 1100 100011 0011 010011 0011 110010 0011 001011 0011 101010 0011 011010 0011 000101 1100 001100 1100 100110 0011 010110 0011 001001 1100 001110 0011 010001 1100 100001 1100 010100 1100 011000 1010 100010 1010
010 00001 010 00010 010 00011 010 00100 010 00101 010 00110 010 00111 010 01000 010 01001 010 01010 010 01011 010 01100 010 01101 010 01110 010 01111 010 10000 010 10001 010 10010 010 10011 010 10100 010 10101 010 10110 010 10111 010 11000 010 11001 010 11010 010 11011 010 11100 010 11101 010 11110 010 11111 100 00000 100 00001
011 00001 011 00010 011 00011 011 00100 011 00101 011 00110 011 00111 011 01000 011 01001 011 01010 011 01011 011 01100 011 01101 011 01110 011 01111 011 10000 011 10001 011 10010 011 10011 011 10100 011 10101 011 10110 011 10111 011 11000 011 11001 011 11010 011 11011 011 11100 011 11101 011 11110 011 11111 101 00000 101 00001
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-5
Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D2.4 D3.4 D4.4 D5.4 D6.4 D7.4 D8.4 D9.4 D10.4 D11.4 D12.4 D13.4 D14.4 D15.4 D16.4 D17.4 D18.4 D19.4 D20.4 D21.4 D22.4 D23.4 D24.4 D25.4 D26.4 D27.4 D28.4 D29.4 D30.4 D31.4 D0.6 D1.6 D2.6 Data Value
HGF EDCBA
Current RDabcdei fghj 101101 0010 110001 1101 110101 0010 101001 1101 011001 1101 111000 1101 111001 0010 100101 1101 010101 1101 110100 1101 001101 1101 101100 1101 011100 1101 010111 0010 011011 0010 100011 1101 010011 1101 110010 1101 001011 1101 101010 1101 011010 1101 111010 0010 110011 0010 100110 1101 010110 1101 110110 0010 001110 1101 101110 0010 011110 0010 101011 0010 100111 0110 011101 0110 101101 0110
Current RD+ abcdei fghj 010010 1101 110001 0010 001010 1101 101001 0010 011001 0010 000111 0010 000110 1101 100101 0010 010101 0010 110100 0010 001101 0010 101100 0010 011100 0010 101000 1101 100100 1101 100011 0010 010011 0010 110010 0010 001011 0010 101010 0010 011010 0010 000101 1101 001100 1101 100110 0010 010110 0010 001001 1101 001110 0010 010001 1101 100001 1101 010100 1101 011000 0110 100010 0110 010010 0110
Data Name D2.5 D3.5 D4.5 D5.5 D6.5 D7.5 D8.5 D9.5 D10.5 D11.5 D12.5 D13.5 D14.5 D15.5 D16.5 D17.5 D18.5 D19.5 D20.5 D21.5 D22.5 D23.5 D24.5 D25.5 D26.5 D27.5 D28.5 D29.5 D30.5 D31.5 D0.7 D1.7 D2.7
Data Value
HGF EDCBA
Current RDabcdei fghj 101101 1010 110001 1010 110101 1010 101001 1010 011001 1010 111000 1010 111001 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 010111 1010 011011 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 010101 1010 111010 1010 110011 1010 100110 1010 010110 1010 110110 1010 001110 1010 101110 1010 011110 1010 101011 1010 100111 0001 011101 0001 101101 0001
Current RD+ abcdei fghj 010010 1010 110001 1010 001010 1010 101001 1010 011001 1010 000111 1010 000110 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 101000 1010 100100 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 011010 1010 000101 1010 001100 1010 100110 1010 010110 1010 001001 1010 001110 1010 010001 1010 100001 1010 010100 1010 011000 1110 100010 1110 010010 1110
100 00010 100 00011 100 00100 100 00101 100 00110 100 00111 100 01000 100 01001 100 01010 100 01011 100 01100 100 01101 100 01110 100 01111 100 10000 100 10001 100 10010 100 10011 100 10100 100 10101 100 10110 100 10111 100 11000 100 11001 100 11010 100 11011 100 11100 100 11101 100 11110 100 11111 110 00000 110 00001 110 00010
101 00010 101 00011 101 00100 101 00101 101 00110 101 00111 101 01000 101 01001 101 01010 101 01011 101 01100 101 01101 101 01110 101 01111 101 10000 101 10001 101 10010 101 10011 101 10100 101 10101 101 10110 101 10111 101 11000 101 11001 101 11010 101 11011 101 11100 101 11101 101 11110 101 11111 111 00000 111 00001 111 00010
B-6
MC92610 SERDES User's Manual
MOTOROLA
Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6 D27.6 D28.6 D29.6 D30.6 D31.6 Data Value
HGF EDCBA
Current RDabcdei fghj 110001 0110 110101 0110 101001 0110 011001 0110 111000 0110 111001 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 010111 0110 011011 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 111010 0110 110011 0110 100110 0110 010110 0110 110110 0110 001110 0110 101110 0110 011110 0110 101011 0110
Current RD+ abcdei fghj 110001 0110 001010 0110 101001 0110 011001 0110 000111 0110 000110 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 101000 0110 100100 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 000101 0110 001100 0110 100110 0110 010110 0110 001001 0110 001110 0110 010001 0110 100001 0110 010100 0110
Data Name D3.7 D4.7 D5.7 D6.7 D7.7 D8.7 D9.7 D10.7 D11.7 D12.7 D13.7 D14.7 D15.7 D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.7 D30.7 D31.7
Data Value
HGF EDCBA
Current RDabcdei fghj 110001 1110 110101 0001 101001 1110 011001 1110 111000 1110 111001 0001 100101 1110 010101 1110 110100 1110 001101 1110 101100 1110 011100 1110 010111 0001 011011 0001 100011 0111 010011 0111 110010 1110 001011 0111 101010 1110 011010 1110 111010 0001 110011 0001 100110 1110 010110 1110 110110 0001 001110 1110 101110 0001 011110 0001 101011 0001
Current RD+ abcdei fghj 110001 0001 001010 1110 101001 0001 011001 0001 000111 0001 000110 1110 100101 0001 010101 0001 110100 1000 001101 0001 101100 1000 011100 1000 101000 1110 100100 1110 100011 0001 010011 0001 110010 0001 001011 0001 101010 0001 011010 0001 000101 1110 001100 1110 100110 0001 010110 0001 001001 1110 001110 0001 010001 1110 100001 1110 010100 1110
110 00011 110 00100 110 00101 110 00110 110 00111 110 01000 110 01001 110 01010 110 01011 110 01100 110 01101 110 01110 110 01111 110 10000 110 10001 110 10010 110 10011 110 10100 110 10101 110 10110 110 10111 110 11000 110 11001 110 11010 110 11011 110 11100 110 11101 110 11110 110 11111
111 00011 111 00100 111 00101 111 00110 111 00111 111 01000 111 01001 111 01010 111 01011 111 01100 111 01101 111 01110 111 01111 111 10000 111 10001 111 10010 111 10011 111 10100 111 10101 111 10110 111 10111 111 11000 111 11001 111 11010 111 11011 111 11100 111 11101 111 11110 111 11111
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-7
Data Tables
Table B-3 displays the full valid special character 8B/10B codes.
Table B-3. Valid Special Characters
Name K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 Data Value
HGF EDCBA
Current RDabcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010
Current RD+ abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101
Name K28.6 K28.7 K23.7 K27.7 K29.7 K30.7
Data Value
HGF EDCBA
Current RDabcdei fghj 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000
Current RD+ abcdie fghj 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111
000 11100 001 11100 010 11100 011 11100 100 11100 101 11100
110 11100 111 11100 111 10111 111 11011 111 11101 111 11110
B-8
MC92610 SERDES User's Manual
MOTOROLA
Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and definitions included in the glossary are reprinted from IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright (c)1985 by the Institute of Electrical and Electronics Engineers, Inc., with the permission of the IEEE.
A B
Asserted. Indicates active state of signal has been set. Refers to either inputs or outputs. BERC. Bit Error Rate Checking. BERT. Bit Error Rate Testing. BIST. Built-In Self-Test. Bit alignment. Refers to the transition tracking loop recovering data bits from the serial input stream. Byte. Eight bits of uncoded data. Byte alignment. Receiver identification of character boundaries through use of Idle character recognition.
C G
Character. An 8B/10B encoded byte of data. Gigabit. A unit of speed of data transfer. One gigabit indicates a data throughput of 1 billion bits per second requiring a transfer rate of 1.25 billion symbols per second of 8B/10B encoded data. Gigabaud. A unit of speed of symbol transfer. One gigabaud indicates a data throughput of 800 million bits per second requiring a transfer rate of 1.0 billion symbols per second of 8B/10B encoded data.
I
ISI. Inter Symbol Interference, a distortion caused by the high-frequency loss characteristics of the transmission media.
MOTOROLA
Glossary
Glossary-1
N P R
Negated. Indicates inactive state of signal has been set. Refers to either inputs or outputs. PLL. Phase Locked Loop. PPM. parts per million. Running disparity. The amount of DC imbalance over a history of symbols transmitted over a link. Equal to the difference between the number of one and zero symbols transmitted. Symbol. One piece of information sent across the link; different from a bit in that bit implies data where symbol is encoded data. Word synchronization. Alignment of four or more receivers' data by adjusting for differences in media and systemic delay between them such that data is presented by the receivers in the same grouping as they were transmit.
S W
Glossary-2
MC92610 SERDES User's Manual
MOTOROLA
Index
Numerics
8B/10B coding scheme, B-1 decoder, 3-13 encoder operation, 2-7 encoder/decoder, 5-5 encoding sequence of, B-2 notation, B-1
E
Electrical Characteristics, 6-1 Specifications, 6-1
F
Features, 1-1 Frequency offset, 3-8, 3-12, 3-16 Functional description, 2-5
A
Absolute Maximum Ratings, 6-1 AC Electrical Characteristics, 6-4 Add/Drop Idle Mode, 4-4 Alignment loss, 3-9
G
General Parameters, 6-1
H
Half-Speed Mode, 3-17, 4-4 HSTL reference voltage recommendation, 4-6
B
BIST Error Codes, 5-5 Boundary-Scan Register, 5-3 Byte alignment, 3-8 Interface, 3-14, 3-15 Byte interface mode, 3-14
I
IEEE Std. 1149.1 Implementation, 5-1 Impedance control reference recommendation, 4-7 Input Amplifier, 3-6 Instruction Register, 5-2 Instructions, 5-2
C
Configuration and Control Signals, 4-4 Conventions, xv
J
JTAG I/O Timing Diagram, 6-10 I/O Timing Specification, 6-10
D
Data Recovery, 3-8 DC Electrical Specifications, 6-3 Device Identification Register, 5-3 Disparity calculating, B-3 Double Data Rate Mode, 4-4
L
Link Differential Input Timing Diagram, 6-9 Input Timing Specification, 6-10 Output Specification, 6-9 Output Timing Diagram, 6-9 Link Multiplexer Mode, 2-6, 3-17
MOTOROLA
Index
Index-1
Loop, 5-6 Loop-Back BIST Sequence System Test Mode, 5-6 Loop-Back Test Mode, 2-8
M
MC92610 Block Diagram, 1-2 Overview, 1-1 Modes Half-Speed Mode, 3-17 Link Multiplexer Mode, 3-17 Recovered Clock Timing Mode, 3-16 Reference Clock Timing Mode, 3-16 Repeater Mode, 3-17
Specification, 6-8 Timing Diagram, 6-8 Timing Mode, 3-16 Reference Clock Specification, 6-8 Timing Diagram, 6-7 Timing Mode, 3-16 References, 1-4 Repeater Mode, 2-7, 3-17 Revision History, 1-4
S
Startup, 4-2
T O
Operating Conditions, 6-2 TAP Interface Signals, 5-1 Ten-Bit Interface, 3-14, 3-15 Ten-Bit Interface Mode, 4-2 Test Access Port Interface Signals, 5-1 Test modes Loop-back BIST Sequence System Test Mode, 5-6 Transition density, B-1 Transition Tracking Loop, 3-8 Transition Tracking Loop and Data Recovery, 3-8 Transmission characters naming, types, B-2 overview, B-1 Transmit Data Input Register Operation, 2-5 Transmit Driver Operation, 2-8 Transmit Equalization, 2-8 Transmit Interface Clock Configuration, 2-7 Transmitter, 2-1 Block Diagram, 2-2 DDR Interface Timing, 6-4 DDR Timing Specification, 6-4 Interface SDR Timing Diagram, 6-5 Interface Signals, 2-2 SDR Timing Specification, 6-5 Transmitter Control States, 2-5 Transmitter Interface Signals, 2-2 Transmitting, 2-5 Transmitting Pre-Coded Data, 2-6 Transmitting Uncoded Data, 2-5
P
Package Description, 7-1 Nomenclature and Dimensions, 7-1 Parameter Summary, 7-1 Pinout Listing, 7-5 Thermal Characteristics, 7-5 Performance, 5-3 Phase Locked Loop (PLL) Power Supply Filtering, 4-5 Pinout Listing, 7-5 Power Supply, 6-1 Power supply decoupling recommendations, 4-6 requirements, 4-5 production testing, 5-1 Proper running disparity, B-2
R
Realignment method, 3-8 Receiver, 3-1 Block Diagram, 3-2 DDR Timing Specification, 6-5 Equalization, 3-7 Functional Description, 3-5 interface, 3-13 Interface DDR Timing Diagram, 6-5 Interface Error Codes, 3-14, 3-15 Interface SDR Timing Diagram, 6-6 Interface Signals, 3-2, 3-3 SDR Timing Specification, 6-6 Recovered Clock Mode, 4-3
U
Uncoded data in 8B/10B coding scheme, B-1
V
Voltage Reference for Single-Ended Reference Clock Use, 4-7
Index-2
MC92610 SERDES User's Manual
MOTOROLA
W
Word Synchronization Bus, 3-11 Bus Timing Diagram, 6-7 Bus Timing Specification, 6-7 Mode, 4-3 States, 3-12
MOTOROLA
Index
Index-3
Index-4
MC92610 SERDES User's Manual
MOTOROLA
Overview Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
1 2 3 4 5 6 7
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
A B GLO IND
1 2 3 4 5 6 7
Overview Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
A B GLO IND
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index

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